8a84c747d2
This is a preliminary step for a preliminary step for D50992. I noticed that x86 often misses chances to load a scalar directly into a vector register. So this patch is just allowing more of those cases to match a broadcast op in lowerBuildVectorAsBroadcast(). The old code comment said it doesn't make sense to use a broadcast when we're loading a single element and everything else is undef, but I think that's the best case in the improved tests in insert-loaded-scalar.ll. We avoid scalar-to-vector-register move and/or less efficient shuffling. Note that there are some existing types that were already producing a broadcast, but that happens semi-accidentally. Ie, it's not happening as part of lowerBuildVectorAsBroadcast(). The build vector gets expanded into load + shuffle, and then shuffle lowering produces the broadcast. Description of the other test diffs: 1. avx-basic.ll - replacing load+shufle is a win. 2. sse3-avx-addsub-2.ll - vmovddup vs. vbroadcastss is neutral 3. sse41.ll - don't care - we convert that intrinsic to generic IR now, so this test is deprecated 4. vector-shuffle-128-v8.ll / vector-shuffle-256-v16.ll - pshufb alternatives with an extra instruction are not obviously bad Differential Revision: https://reviews.llvm.org/D51125 llvm-svn: 340685
444 lines
13 KiB
LLVM
444 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX,AVX2
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define <16 x i8> @load8_ins_elt0_v16i8(i8* %p) nounwind {
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; SSE-LABEL: load8_ins_elt0_v16i8:
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; SSE: # %bb.0:
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; SSE-NEXT: movzbl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load8_ins_elt0_v16i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movzbl (%rdi), %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load8_ins_elt0_v16i8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastb (%rdi), %xmm0
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; AVX2-NEXT: retq
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%x = load i8, i8* %p
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%ins = insertelement <16 x i8> undef, i8 %x, i32 0
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ret <16 x i8> %ins
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}
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define <8 x i16> @load16_ins_elt0_v8i16(i16* %p) nounwind {
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; SSE-LABEL: load16_ins_elt0_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movzwl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load16_ins_elt0_v8i16:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movzwl (%rdi), %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load16_ins_elt0_v8i16:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastw (%rdi), %xmm0
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; AVX2-NEXT: retq
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%x = load i16, i16* %p
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%ins = insertelement <8 x i16> undef, i16 %x, i32 0
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ret <8 x i16> %ins
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}
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define <4 x i32> @load32_ins_elt0_v4i32(i32* %p) nounwind {
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; SSE-LABEL: load32_ins_elt0_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load32_ins_elt0_v4i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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%x = load i32, i32* %p
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%ins = insertelement <4 x i32> undef, i32 %x, i32 0
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ret <4 x i32> %ins
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}
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define <2 x i64> @load64_ins_elt0_v2i64(i64* %p) nounwind {
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; SSE-LABEL: load64_ins_elt0_v2i64:
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; SSE: # %bb.0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load64_ins_elt0_v2i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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%x = load i64, i64* %p
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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ret <2 x i64> %ins
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}
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define <4 x float> @load32_ins_elt0_v4f32(float* %p) nounwind {
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; SSE-LABEL: load32_ins_elt0_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load32_ins_elt0_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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%x = load float, float* %p
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%ins = insertelement <4 x float> undef, float %x, i32 0
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ret <4 x float> %ins
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}
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define <2 x double> @load64_ins_elt0_v2f64(double* %p) nounwind {
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; SSE-LABEL: load64_ins_elt0_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load64_ins_elt0_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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%x = load double, double* %p
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%ins = insertelement <2 x double> undef, double %x, i32 0
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ret <2 x double> %ins
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}
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define <16 x i8> @load8_ins_eltc_v16i8(i8* %p) nounwind {
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; SSE-LABEL: load8_ins_eltc_v16i8:
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; SSE: # %bb.0:
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; SSE-NEXT: movzbl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: pslld $24, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load8_ins_eltc_v16i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movzbl (%rdi), %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: vpslld $24, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load8_ins_eltc_v16i8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastb (%rdi), %xmm0
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; AVX2-NEXT: retq
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%x = load i8, i8* %p
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%ins = insertelement <16 x i8> undef, i8 %x, i32 3
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ret <16 x i8> %ins
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}
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define <8 x i16> @load16_ins_eltc_v8i16(i16* %p) nounwind {
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; SSE-LABEL: load16_ins_eltc_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movzwl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load16_ins_eltc_v8i16:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movzwl (%rdi), %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load16_ins_eltc_v8i16:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastw (%rdi), %xmm0
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; AVX2-NEXT: retq
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%x = load i16, i16* %p
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%ins = insertelement <8 x i16> undef, i16 %x, i32 5
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ret <8 x i16> %ins
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}
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define <4 x i32> @load32_ins_eltc_v4i32(i32* %p) nounwind {
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; SSE-LABEL: load32_ins_eltc_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load32_ins_eltc_v4i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss (%rdi), %xmm0
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; AVX-NEXT: retq
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%x = load i32, i32* %p
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%ins = insertelement <4 x i32> undef, i32 %x, i32 2
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ret <4 x i32> %ins
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}
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define <2 x i64> @load64_ins_eltc_v2i64(i64* %p) nounwind {
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; SSE-LABEL: load64_ins_eltc_v2i64:
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; SSE: # %bb.0:
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; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load64_ins_eltc_v2i64:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load64_ins_eltc_v2i64:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastq (%rdi), %xmm0
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; AVX2-NEXT: retq
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%x = load i64, i64* %p
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%ins = insertelement <2 x i64> undef, i64 %x, i32 1
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ret <2 x i64> %ins
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}
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define <4 x float> @load32_ins_eltc_v4f32(float* %p) nounwind {
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; SSE-LABEL: load32_ins_eltc_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,2,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load32_ins_eltc_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss (%rdi), %xmm0
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; AVX-NEXT: retq
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%x = load float, float* %p
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%ins = insertelement <4 x float> undef, float %x, i32 3
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ret <4 x float> %ins
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}
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define <2 x double> @load64_ins_eltc_v2f64(double* %p) nounwind {
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; SSE-LABEL: load64_ins_eltc_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load64_ins_eltc_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
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; AVX-NEXT: retq
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%x = load double, double* %p
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%ins = insertelement <2 x double> undef, double %x, i32 1
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ret <2 x double> %ins
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}
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define <32 x i8> @load8_ins_elt0_v32i8(i8* %p) nounwind {
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; SSE-LABEL: load8_ins_elt0_v32i8:
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; SSE: # %bb.0:
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; SSE-NEXT: movzbl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load8_ins_elt0_v32i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movzbl (%rdi), %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load8_ins_elt0_v32i8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastb (%rdi), %ymm0
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; AVX2-NEXT: retq
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%x = load i8, i8* %p
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%ins = insertelement <32 x i8> undef, i8 %x, i32 0
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ret <32 x i8> %ins
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}
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define <16 x i16> @load16_ins_elt0_v16i16(i16* %p) nounwind {
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; SSE-LABEL: load16_ins_elt0_v16i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movzwl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load16_ins_elt0_v16i16:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movzwl (%rdi), %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load16_ins_elt0_v16i16:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastw (%rdi), %ymm0
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; AVX2-NEXT: retq
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%x = load i16, i16* %p
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%ins = insertelement <16 x i16> undef, i16 %x, i32 0
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ret <16 x i16> %ins
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}
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define <8 x i32> @load32_ins_elt0_v8i32(i32* %p) nounwind {
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; SSE-LABEL: load32_ins_elt0_v8i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load32_ins_elt0_v8i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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%x = load i32, i32* %p
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%ins = insertelement <8 x i32> undef, i32 %x, i32 0
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ret <8 x i32> %ins
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}
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define <4 x i64> @load64_ins_elt0_v4i64(i64* %p) nounwind {
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; SSE-LABEL: load64_ins_elt0_v4i64:
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; SSE: # %bb.0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load64_ins_elt0_v4i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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%x = load i64, i64* %p
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%ins = insertelement <4 x i64> undef, i64 %x, i32 0
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ret <4 x i64> %ins
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}
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define <8 x float> @load32_ins_elt0_v8f32(float* %p) nounwind {
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; SSE-LABEL: load32_ins_elt0_v8f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load32_ins_elt0_v8f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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%x = load float, float* %p
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%ins = insertelement <8 x float> undef, float %x, i32 0
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ret <8 x float> %ins
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}
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define <4 x double> @load64_ins_elt0_v4f64(double* %p) nounwind {
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; SSE-LABEL: load64_ins_elt0_v4f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load64_ins_elt0_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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%x = load double, double* %p
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%ins = insertelement <4 x double> undef, double %x, i32 0
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ret <4 x double> %ins
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}
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define <32 x i8> @load8_ins_eltc_v32i8(i8* %p) nounwind {
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; SSE-LABEL: load8_ins_eltc_v32i8:
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; SSE: # %bb.0:
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; SSE-NEXT: movzbl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm1
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; SSE-NEXT: psllq $40, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load8_ins_eltc_v32i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movzbl (%rdi), %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: vpsllq $40, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: load8_ins_eltc_v32i8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastb (%rdi), %ymm0
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; AVX2-NEXT: retq
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%x = load i8, i8* %p
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%ins = insertelement <32 x i8> undef, i8 %x, i32 21
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ret <32 x i8> %ins
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}
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define <16 x i16> @load16_ins_eltc_v16i16(i16* %p) nounwind {
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; SSE-LABEL: load16_ins_eltc_v16i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movzwl (%rdi), %eax
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; SSE-NEXT: movd %eax, %xmm1
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; SSE-NEXT: psllq $48, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: load16_ins_eltc_v16i16:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: movzwl (%rdi), %eax
|
|
; AVX1-NEXT: vmovd %eax, %xmm0
|
|
; AVX1-NEXT: vpsllq $48, %xmm0, %xmm0
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: load16_ins_eltc_v16i16:
|
|
; AVX2: # %bb.0:
|
|
; AVX2-NEXT: vpbroadcastw (%rdi), %ymm0
|
|
; AVX2-NEXT: retq
|
|
%x = load i16, i16* %p
|
|
%ins = insertelement <16 x i16> undef, i16 %x, i32 11
|
|
ret <16 x i16> %ins
|
|
}
|
|
|
|
define <8 x i32> @load32_ins_eltc_v8i32(i32* %p) nounwind {
|
|
; SSE-LABEL: load32_ins_eltc_v8i32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,2,0]
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: load32_ins_eltc_v8i32:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vbroadcastss (%rdi), %ymm0
|
|
; AVX-NEXT: retq
|
|
%x = load i32, i32* %p
|
|
%ins = insertelement <8 x i32> undef, i32 %x, i32 7
|
|
ret <8 x i32> %ins
|
|
}
|
|
|
|
define <4 x i64> @load64_ins_eltc_v4i64(i64* %p) nounwind {
|
|
; SSE-LABEL: load64_ins_eltc_v4i64:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
|
|
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: load64_ins_eltc_v4i64:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
; AVX-NEXT: retq
|
|
%x = load i64, i64* %p
|
|
%ins = insertelement <4 x i64> undef, i64 %x, i32 3
|
|
ret <4 x i64> %ins
|
|
}
|
|
|
|
define <8 x float> @load32_ins_eltc_v8f32(float* %p) nounwind {
|
|
; SSE-LABEL: load32_ins_eltc_v8f32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
; SSE-NEXT: movsldup {{.*#+}} xmm1 = xmm0[0,0,2,2]
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: load32_ins_eltc_v8f32:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vbroadcastss (%rdi), %ymm0
|
|
; AVX-NEXT: retq
|
|
%x = load float, float* %p
|
|
%ins = insertelement <8 x float> undef, float %x, i32 5
|
|
ret <8 x float> %ins
|
|
}
|
|
|
|
define <4 x double> @load64_ins_eltc_v4f64(double* %p) nounwind {
|
|
; SSE-LABEL: load64_ins_eltc_v4f64:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movddup {{.*#+}} xmm1 = mem[0,0]
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: load64_ins_eltc_v4f64:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
; AVX-NEXT: retq
|
|
%x = load double, double* %p
|
|
%ins = insertelement <4 x double> undef, double %x, i32 3
|
|
ret <4 x double> %ins
|
|
}
|
|
|