eb0c510ecd
Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters that cover the low halves of these registers. This change adds artificial subregisters for the high halves in order to differentiate (in terms of register units) between the 32- and the low 16-bit registers. This patch contains parts that aim to preserve the calculated register pressure. This is in order to preserve the current codegen (minimize the impact of this patch). The approach of having artificial subregisters could be used to fix PR23423, but the pressure calculation would need to be changed. Differential Revision: https://reviews.llvm.org/D43353 llvm-svn: 328016
13 lines
384 B
LLVM
13 lines
384 B
LLVM
; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
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target triple = "x86_64--"
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define i8 @main(i8 %X) {
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%inc = add i8 %X, 1
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%inc2 = mul i8 %inc, 5
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; Here only CL is clobbred so CH should not be clobbred, but CX, ECX and RCX
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; should be clobbered.
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; CHECK: main Clobbered Registers: $ah $al $ax $cl $cx $eax $ecx $eflags $hax $rax $rcx
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ret i8 %inc2
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}
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