ee4bfcaa5a
Setting the right SDLoc on a newly-created zextload fixes a line table bug which resulted in non-linear stepping behavior. Several backend tests contained CHECK lines which relied on the IROrder inherited from the wrong SDLoc. This patch breaks that dependence where feasbile and regenerates test cases where not. In some cases, changing a node's IROrder may alter register allocation and spill behavior. This can affect performance. I have chosen not to prevent this by applying a "known good" IROrder to SDLocs, as this may hide a more general bug in the scheduler, or cause regressions on other test inputs. rdar://33755881, Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D45995 llvm-svn: 331300
30 lines
844 B
LLVM
30 lines
844 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+bmi2 | FileCheck %s
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=core-avx2 | FileCheck %s
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define i64 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: mulxl {{[0-9]+}}(%esp), %eax, %edx
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; CHECK-NEXT: retl
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%x = zext i32 %a to i64
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%y = zext i32 %b to i64
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%r = mul i64 %x, %y
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ret i64 %r
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}
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define i64 @f2(i32 %a, i32* %p) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: mulxl (%eax), %eax, %edx
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; CHECK-NEXT: retl
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%b = load i32, i32* %p
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%x = zext i32 %a to i64
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%y = zext i32 %b to i64
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%r = mul i64 %x, %y
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ret i64 %r
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}
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