8238580aae
In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order.
This patch removes the hack.
This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage.
Differential Revision: https://reviews.llvm.org/D49499
llvm-svn: 341973
107 lines
3.3 KiB
LLVM
107 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=core-avx-i | FileCheck %s --check-prefix=AVX
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define <2 x double> @v2f2d_ext_vec(<2 x float> %v1) nounwind {
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; SSE-LABEL: v2f2d_ext_vec:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: cvtps2pd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v2f2d_ext_vec:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtps2pd %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%f1 = fpext <2 x float> %v1 to <2 x double>
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ret <2 x double> %f1
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}
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define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind {
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; SSE-LABEL: v3f2d_ext_vec:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: cvtps2pd %xmm0, %xmm2
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; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSE-NEXT: cvtps2pd %xmm0, %xmm0
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; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movaps %xmm2, %xmm1
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; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]
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; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v3f2d_ext_vec:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtps2pd %xmm0, %ymm0
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; AVX-NEXT: retq
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entry:
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%f1 = fpext <3 x float> %v1 to <3 x double>
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ret <3 x double> %f1
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}
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define <4 x double> @v4f2d_ext_vec(<4 x float> %v1) nounwind {
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; SSE-LABEL: v4f2d_ext_vec:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: cvtps2pd %xmm0, %xmm2
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; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSE-NEXT: cvtps2pd %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v4f2d_ext_vec:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtps2pd %xmm0, %ymm0
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; AVX-NEXT: retq
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entry:
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%f1 = fpext <4 x float> %v1 to <4 x double>
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ret <4 x double> %f1
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}
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define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind {
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; SSE-LABEL: v8f2d_ext_vec:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: cvtps2pd %xmm0, %xmm5
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; SSE-NEXT: cvtps2pd %xmm1, %xmm2
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; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSE-NEXT: cvtps2pd %xmm0, %xmm4
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; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
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; SSE-NEXT: cvtps2pd %xmm1, %xmm3
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; SSE-NEXT: movaps %xmm5, %xmm0
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; SSE-NEXT: movaps %xmm4, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v8f2d_ext_vec:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtps2pd %xmm0, %ymm2
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX-NEXT: vcvtps2pd %xmm0, %ymm1
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; AVX-NEXT: vmovaps %ymm2, %ymm0
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; AVX-NEXT: retq
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entry:
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%f1 = fpext <8 x float> %v1 to <8 x double>
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ret <8 x double> %f1
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}
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define void @test_vector_creation() nounwind {
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; SSE-LABEL: test_vector_creation:
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; SSE: # %bb.0:
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; SSE-NEXT: xorpd %xmm0, %xmm0
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; SSE-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
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; SSE-NEXT: movapd %xmm0, (%rax)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_vector_creation:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
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; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX-NEXT: vmovaps %ymm0, (%rax)
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%1 = insertelement <4 x double> undef, double 0.000000e+00, i32 2
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%2 = load double, double addrspace(1)* null
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%3 = insertelement <4 x double> %1, double %2, i32 3
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store <4 x double> %3, <4 x double>* undef
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ret void
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}
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