0423881820
These instructions perform the same operation, but the semantic of which operand is destroyed is reversed. If the same register is used as both operands we can change the execution domain without worrying about this difference. Unfortunately, this really only works in cases where the input register is killed by the instruction. If its not killed, the two address isntruction pass inserts a copy that will become a move instruction. This makes the instruction use different physical registers that contain the same data at the time the unpck/movhlps executes. I've considered using a unary pseudo instruction with tied operand to trick the two address instruction pass. We could then expand the pseudo post regalloc to get the same physical register on both inputs. Differential Revision: https://reviews.llvm.org/D50157 llvm-svn: 338735
136 lines
5.1 KiB
LLVM
136 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+sse2 -mcpu=nehalem | FileCheck %s
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; rdar: 12558838
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; PR14221
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; There is a mismatch between the intrinsic and the actual instruction.
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; The actual instruction has a partial update of dest, while the intrinsic
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; passes through the upper FP values. Here, we make sure the source and
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; destination of each scalar unary op are the same.
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define void @rsqrtss(<4 x float> %a) nounwind uwtable ssp {
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; CHECK-LABEL: rsqrtss:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: rsqrtss %xmm0, %xmm0
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; CHECK-NEXT: cvtss2sd %xmm0, %xmm2
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; CHECK-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; CHECK-NEXT: cvtss2sd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm2, %xmm0
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; CHECK-NEXT: jmp _callee ## TAILCALL
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entry:
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%0 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a) nounwind
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%a.addr.0.extract = extractelement <4 x float> %0, i32 0
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%conv = fpext float %a.addr.0.extract to double
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%a.addr.4.extract = extractelement <4 x float> %0, i32 1
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%conv3 = fpext float %a.addr.4.extract to double
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tail call void @callee(double %conv, double %conv3) nounwind
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ret void
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}
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declare void @callee(double, double)
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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define void @rcpss(<4 x float> %a) nounwind uwtable ssp {
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; CHECK-LABEL: rcpss:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: rcpss %xmm0, %xmm0
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; CHECK-NEXT: cvtss2sd %xmm0, %xmm2
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; CHECK-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; CHECK-NEXT: cvtss2sd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm2, %xmm0
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; CHECK-NEXT: jmp _callee ## TAILCALL
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entry:
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%0 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a) nounwind
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%a.addr.0.extract = extractelement <4 x float> %0, i32 0
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%conv = fpext float %a.addr.0.extract to double
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%a.addr.4.extract = extractelement <4 x float> %0, i32 1
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%conv3 = fpext float %a.addr.4.extract to double
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tail call void @callee(double %conv, double %conv3) nounwind
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ret void
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}
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define void @sqrtss(<4 x float> %a) nounwind uwtable ssp {
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; CHECK-LABEL: sqrtss:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: sqrtss %xmm0, %xmm1
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; CHECK-NEXT: cvtss2sd %xmm1, %xmm2
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; CHECK-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; CHECK-NEXT: xorps %xmm1, %xmm1
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; CHECK-NEXT: cvtss2sd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm2, %xmm0
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; CHECK-NEXT: jmp _callee ## TAILCALL
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entry:
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%0 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a) nounwind
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%a.addr.0.extract = extractelement <4 x float> %0, i32 0
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%conv = fpext float %a.addr.0.extract to double
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%a.addr.4.extract = extractelement <4 x float> %0, i32 1
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%conv3 = fpext float %a.addr.4.extract to double
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tail call void @callee(double %conv, double %conv3) nounwind
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ret void
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}
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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define void @sqrtsd(<2 x double> %a) nounwind uwtable ssp {
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; CHECK-LABEL: sqrtsd:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: sqrtsd %xmm0, %xmm1
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; CHECK-NEXT: cvtsd2ss %xmm1, %xmm2
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; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
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; CHECK-NEXT: xorps %xmm1, %xmm1
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; CHECK-NEXT: cvtsd2ss %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm2, %xmm0
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; CHECK-NEXT: jmp _callee2 ## TAILCALL
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entry:
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%0 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a) nounwind
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%a0 = extractelement <2 x double> %0, i32 0
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%conv = fptrunc double %a0 to float
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%a1 = extractelement <2 x double> %0, i32 1
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%conv3 = fptrunc double %a1 to float
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tail call void @callee2(float %conv, float %conv3) nounwind
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ret void
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}
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declare void @callee2(float, float)
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define <2 x double> @load_fold_cvtss2sd_int(<4 x float> *%a) {
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; CHECK-LABEL: load_fold_cvtss2sd_int:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: cvtss2sd %xmm0, %xmm0
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; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; CHECK-NEXT: retq
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%ld = load <4 x float>, <4 x float> *%a
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%x = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %ld)
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ret <2 x double> %x
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}
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define <2 x double> @load_fold_cvtss2sd_int_optsize(<4 x float> *%a) optsize {
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; CHECK-LABEL: load_fold_cvtss2sd_int_optsize:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: cvtss2sd (%rdi), %xmm0
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; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; CHECK-NEXT: retq
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%ld = load <4 x float>, <4 x float> *%a
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%x = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %ld)
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ret <2 x double> %x
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}
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define <2 x double> @load_fold_cvtss2sd_int_minsize(<4 x float> *%a) minsize {
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; CHECK-LABEL: load_fold_cvtss2sd_int_minsize:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: cvtss2sd (%rdi), %xmm0
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; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; CHECK-NEXT: retq
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%ld = load <4 x float>, <4 x float> *%a
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%x = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %ld)
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ret <2 x double> %x
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}
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declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
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