LDM/STM instructions can run one cycle faster on some ARM processors if the memory address is 64-bit aligned. Radar 8489376. llvm-svn: 115047
58 KiB
58 KiB
LDM/STM instructions can run one cycle faster on some ARM processors if the memory address is 64-bit aligned. Radar 8489376. llvm-svn: 115047