Evan Cheng 05f13e94bf Correct some load / store instruction itinerary mistakes: ...

1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

llvm-svn: 116134

2010-10-09 01:03:04 +00:00

..

Alpha

PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually

2010-08-01 21:13:28 +00:00

ARM

Correct some load / store instruction itinerary mistakes:

2010-10-09 01:03:04 +00:00

Blackfin

Remove TargetInstrInfo::copyRegToReg entirely.

2010-07-11 17:01:17 +00:00

CBackend

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CellSPU

Zap some redundant 'ori $?, $?, 0' from SPU.

2010-10-01 09:20:01 +00:00

CPP

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Generic

Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself

2010-07-27 18:02:18 +00:00

MBlaze

Split big test into multiple directories to cater to

2010-04-07 20:43:35 +00:00

Mips

Enable machine sinking critical edge splitting. e.g.

2010-09-20 22:52:00 +00:00

MSP430

CombinerAA is now reordering these stores.

2010-09-20 20:56:29 +00:00

PIC16

Remove XFAIL for vg_leak as the leaks are fixed by 100601.

2010-04-07 07:06:48 +00:00

PowerPC

the latest assembler that runs on powerpc 10.4 machines doesn't

2010-09-27 06:44:54 +00:00

PTX

Add test case for PTX ret instruction

2010-09-25 07:49:54 +00:00

SPARC

Split big test into multiple directories to cater to

2010-04-07 20:43:35 +00:00

SystemZ

Correct bogus module triple specifications.

2010-08-30 10:48:29 +00:00

Thumb

Try again to disable critical edge splitting in CodeGenPrepare.

2010-09-30 20:51:52 +00:00

Thumb2

Change register allocation order for ARM VFP and NEON registers to put the

2010-10-08 06:15:13 +00:00

X86

Recommit 116056, now with the missing file...

2010-10-08 19:24:18 +00:00

XCore

Enable machine sinking critical edge splitting. e.g.

2010-09-20 22:52:00 +00:00

thumb2-mul.ll

Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes

2010-09-21 22:51:46 +00:00