Ashley Nelson 47f0f8ca47 [WebAssembly] Add exp10 libcall signatures (#69661) ...

The llvm.exp.* family of intrinsics and their corresponding libcalls
were recently added, which means we need to know their signatures.

2023-10-20 12:15:48 -07:00

..

AArch64

[AArch64][GlobalISel] Fix miscompile on carry-in selection (#68840)

2023-10-19 19:50:46 +02:00

AMDGPU

[AMDGPU] Segregate 16-bit fix-sgpr-copies tests. (#69353)

2023-10-20 14:09:30 +01:00

ARC

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ARM

[ARM] Lower i1 concat via MVETRUNC

2023-10-18 19:40:11 +01:00

AVR

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

BPF

Revert "Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size"

2023-10-16 12:17:24 +02:00

CSKY

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

DirectX

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Generic

[AsmPrint] Correctly factor function entry count when dumping MBB frequencies (#67826)

2023-09-29 18:06:53 -07:00

Hexagon

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

Inputs

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Lanai

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LoongArch

[LoongArch] Improve codegen for atomic cmpxchg ops (#69339)

2023-10-19 09:21:51 +08:00

M68k

[M68k] Add new calling convention M68k_RTD

2023-10-15 16:12:31 -07:00

Mips

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

MIR

[YAMLParser] Improve plain scalar spec compliance (#68946)

2023-10-17 11:28:14 -06:00

MLRegAlloc

[mlgo] Fix tests post 760e7d0

2023-10-17 12:19:54 -07:00

MSP430

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

NVPTX

[NVPTX] Preserve v16i8 vector loads when legalizing

2023-10-19 12:34:25 +01:00

PowerPC

ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (#66924)

2023-10-19 13:05:04 +01:00

RISCV

[RISCV][GISel] Support G_PTRTOINT and G_INTTOPTR (#69542)

2023-10-20 12:03:09 -07:00

SPARC

[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) (#66851)

2023-10-10 20:34:20 +03:00

SPIRV

[SPIR-V] Emit proper pointer type for OpenCL kernel arguments (#67726)

2023-10-18 20:51:53 -07:00

SystemZ

[SystemZ] Support builtin_{frame,return}_address() with non-zero argument (#69405)

2023-10-18 19:05:31 +02:00

Thumb

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

Thumb2

[ARM] Lower i1 concat via MVETRUNC

2023-10-18 19:40:11 +01:00

VE

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

WebAssembly

[WebAssembly] Add exp10 libcall signatures (#69661)

2023-10-20 12:15:48 -07:00

WinCFGuard

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WinEH

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X86

[Peephole] Check instructions from CopyMIs are still COPY (#69511)

2023-10-20 08:34:43 -07:00

XCore

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