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clang-p2996/llvm/test/CodeGen/PowerPC
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Ramkumar Ramachandra 98c90a13c6 ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (#66924) 
The issue #55208 noticed that std::rint is vectorized by the
SLPVectorizer, but a very similar function, std::lrint, is not.
std::lrint corresponds to ISD::LRINT in the SelectionDAG, and
std::llrint is a familiar cousin corresponding to ISD::LLRINT. Now,
neither ISD::LRINT nor ISD::LLRINT have a corresponding vector variant,
and the LangRef makes this clear in the documentation of llvm.lrint.*
and llvm.llrint.*.

This patch extends the LangRef to include vector variants of
llvm.lrint.* and llvm.llrint.*, and lays the necessary ground-work of
scalarizing it for all targets. However, this patch would be devoid of
motivation unless we show the utility of these new vector variants.
Hence, the RISCV target has been chosen to implement a custom lowering
to the vfcvt.x.f.v instruction. The patch also includes a CostModel for
RISCV, and a trivial follow-up can potentially enable the SLPVectorizer
to vectorize std::lrint and std::llrint, fixing #55208.

The patch includes tests, obviously for the RISCV target, but also for
the X86, AArch64, and PowerPC targets to justify the addition of the
vector variants to the LangRef.
2023-10-19 13:05:04 +01:00
..
GlobalISel
[PowerPC][GISel] Add initial GlobalISel support for vector functions.
2023-03-27 08:23:05 -05:00
2004-11-29-ShrCrash.ll
…
2004-11-30-shift-crash.ll
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2004-11-30-shr-var-crash.ll
…
2004-12-12-ZeroSizeCommon.ll
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2005-01-14-SetSelectCrash.ll
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2005-01-14-UndefLong.ll
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2005-08-12-rlwimi-crash.ll
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2005-09-02-LegalizeDuplicatesCalls.ll
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2005-10-08-ArithmeticRotate.ll
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2005-11-30-vastart-crash.ll
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2006-01-11-darwin-fp-argument.ll
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2006-01-20-ShiftPartsCrash.ll
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2006-04-01-FloatDoubleExtend.ll
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2006-04-05-splat-ish.ll
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2006-04-19-vmaddfp-crash.ll
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2006-05-12-rlwimi-crash.ll
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2006-07-07-ComputeMaskedBits.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
2006-07-19-stwbrx-crash.ll
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2006-08-11-RetVector.ll
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2006-08-15-SelectionCrash.ll
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2006-09-28-shift_64.ll
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2006-10-13-Miscompile.ll
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2006-10-17-brcc-miscompile.ll
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2006-10-17-ppc64-alloca.ll
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2006-11-10-DAGCombineMiscompile.ll
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2006-11-29-AltivecFPSplat.ll
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2006-12-07-LargeAlloca.ll
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2006-12-07-SelectCrash.ll
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2007-01-04-ArgExtension.ll
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2007-01-15-AsmDialect.ll
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2007-01-29-lbrx-asm.ll
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2007-01-31-InlineAsmAddrMode.ll
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2007-02-16-AlignPacked.ll
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2007-02-16-InlineAsmNConstraint.ll
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2007-02-23-lr-saved-twice.ll
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2007-03-24-cntlzd.ll
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2007-03-30-SpillerCrash.ll
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2007-04-24-InlineAsm-I-Modifier.ll
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2007-04-30-InlineAsmEarlyClobber.ll
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2007-05-03-InlineAsm-S-Constraint.ll
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2007-05-14-InlineAsmSelectCrash.ll
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2007-05-22-tailmerge-3.ll
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2007-05-30-dagcombine-miscomp.ll
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2007-06-28-BCCISelBug.ll
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2007-08-04-CoalescerAssert.ll
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2007-09-04-AltivecDST.ll
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2007-09-07-LoadStoreIdxForms.ll
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2007-09-08-unaligned.ll
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2007-09-11-RegCoalescerAssert.ll
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2007-09-12-LiveIntervalsAssert.ll
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2007-10-16-InlineAsmFrameOffset.ll
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2007-10-18-PtrArithmetic.ll
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2007-10-21-LocalRegAllocAssert2.ll
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2007-10-21-LocalRegAllocAssert.ll
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2007-11-04-CoalescerCrash.ll
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2007-11-16-landingpad-split.ll
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2007-11-19-VectorSplitting.ll
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2008-02-05-LiveIntervalsAssert.ll
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2008-02-09-LocalRegAllocAssert.ll
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2008-03-05-RegScavengerAssert.ll
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2008-03-17-RegScavengerCrash.ll
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2008-03-18-RegScavengerAssert.ll
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2008-03-24-AddressRegImm.ll
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2008-03-24-CoalescerBug.ll
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2008-03-26-CoalescerBug.ll
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2008-04-10-LiveIntervalCrash.ll
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2008-04-16-CoalescerBug.ll
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2008-04-23-CoalescerCrash.ll
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2008-05-01-ppc_fp128.ll
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2008-06-19-LegalizerCrash.ll
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2008-06-21-F128LoadStore.ll
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2008-06-23-LiveVariablesCrash.ll
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2008-07-10-SplatMiscompile.ll
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2008-07-15-Bswap.ll
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2008-07-15-Fabs.ll
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2008-07-15-SignExtendInreg.ll
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2008-07-17-Fneg.ll
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2008-07-24-PPC64-CCBug.ll
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2008-09-12-CoalescerBug.ll
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2008-10-17-AsmMatchingOperands.ll
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2008-10-28-f128-i32.ll
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2008-10-28-UnprocessedNode.ll
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2008-12-02-LegalizeTypeAssert.ll
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2009-01-16-DeclareISelBug.ll
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2009-03-17-LSRBug.ll
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2009-05-28-LegalizeBRCC.ll
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2009-07-16-InlineAsm-M-Operand.ll
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2009-08-17-inline-asm-addr-mode-breakage.ll
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2009-09-18-carrybit.ll
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2009-11-15-ProcImpDefsBug.ll
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2009-11-25-ImpDefBug.ll
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2010-02-04-EmptyGlobal.ll
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2010-02-12-saveCR.ll
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2010-03-09-indirect-call.ll
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2010-04-01-MachineCSEBug.ll
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2010-05-03-retaddr1.ll
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2010-10-11-Fast-Varargs.ll
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2010-12-18-PPCStackRefs.ll
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2011-12-05-NoSpillDupCR.ll
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2011-12-06-SpillAndRestoreCR.ll
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2011-12-08-DemandedBitsMiscompile.ll
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2012-09-16-TOC-entry-check.ll
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2012-10-11-dynalloc.ll
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2012-10-12-bitcast.ll
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2012-11-16-mischedcall.ll
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2013-05-15-preinc-fold.ll
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2013-07-01-PHIElimBug.mir
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2016-01-07-BranchWeightCrash.ll
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2016-04-16-ADD8TLS.ll
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2016-04-17-combine.ll
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2016-04-28-setjmp.ll
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2018-09-19-sextinreg-vector-crash.ll
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a2-fp-basic.ll
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aa-tbaa.ll
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aantidep-def-ec.mir
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aantidep-inline-asm-use.ll
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absol-jump-table-enabled.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
add_cmp.ll
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add-fi.ll
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addc.ll
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adde_return_type.ll
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addegluecrash.ll
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addi-licm.ll
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addi-offset-fold.ll
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addi-reassoc.ll
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addisdtprelha-nonr3.mir
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addrfuncstr.ll
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addrspacecast.ll
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addze.ll
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aggressive-anti-dep-breaker-subreg.ll
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aix32-cc-abi-vaarg.ll
[DAGCombine] Make sure combined nodes are added back to the worklist in topological order.
2023-06-13 09:14:37 +00:00
aix32-crsave.mir
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aix32-p8-scalar_vector_conversions.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
aix32-vector-pair-cc-spills.ll
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aix32-vector-vararg-callee-split.ll
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aix32-vector-vararg-callee.ll
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aix32-vector-vararg-caller-split.ll
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aix32-vector-vararg-fixed-callee.ll
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aix64-cc-abi-vaarg.ll
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aix64-cc-byval.ll
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aix64-vector-pair-cc-spills.ll
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aix64-vector-vararg-callee.ll
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aix64-vector-vararg-fixed-callee.ll
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aix64-virtual-call-no-spills.ll
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aix64-xcoff-roptr.ll
[AIX][CodeGen] Renaming mroptr to xcoff-mroptr
2023-03-31 10:09:48 -04:00
aix_scalar_vector_permuted.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
aix-alias-alignment-2.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-alias-alignment-3.ll
…
aix-alias-alignment.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-alias-unsupported.ll
…
aix-alias.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-alloca-r31.ll
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aix-AppendingLinkage.ll
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aix-aux-header.ll
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aix-available-externally-linkage-fun.ll
[XCOFF] Enable available_externally linkage for functions.
2023-07-25 22:47:11 -04:00
aix-available-externally-linkage.ll
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aix-base-pointer.ll
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aix-bytestring.ll
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aix-calleesavedregs.ll
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aix-cc-abi.ll
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aix-cc-altivec.ll
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aix-cc-byval-limitation3.ll
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aix-cc-byval-mem.ll
[AIX] Lower some memory intrinsics to millicode functions on AIX
2023-02-20 22:25:49 -05:00
aix-cc-byval-split.ll
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aix-cc-byval.ll
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
aix-cc-ext-vec-abi.ll
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aix-command-line-metadata.ll
Implement -frecord-command-line for XCOFF integrated assembler path
2023-07-20 09:45:37 -04:00
aix-common.ll
[XCOFF][AIX] Issue an error when specifying an alias for a common symbol
2023-08-31 11:43:47 -04:00
aix-complex.ll
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aix-constant-align.ll
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aix-crspill.ll
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aix-csr-alloc.ll
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aix-csr-vector-extabi.ll
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aix-csr-vector.ll
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aix-csr.ll
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aix-dfltabi-rsrvd-reg.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
aix-dwarf.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-ehinfo-sym.ll
…
aix-emit-tracebacktable-clobber-register.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-emit-tracebacktable-redzone-boundary.mir
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-emit-tracebacktable-ssp.ll
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aix-emit-tracebacktable-vectorinfo_hasvarg.ll
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-emit-tracebacktable-vectorinfo.ll
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-emit-tracebacktable.ll
[AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame
2023-03-16 15:26:12 -04:00
aix-exception.ll
…
aix-extern-weak.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-extern.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-external-sym-sdnode-lowering.ll
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aix-filename-absolute-path.ll
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aix-filename-c.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-filename-cpp.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-filename-f.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-filename-relative-path.ll
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aix-filename-special-character-double-quotation.ll
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aix-filename-special-character-single-quotation.ll
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aix-fptoint.ll
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aix-framepointer-save-restore.ll
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aix-func-align.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-func-dsc-gen.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-ignore-xcoff-visibility.ll
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aix-indirect-call.ll
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aix-inlineasm-reserved-reg-dflt-warn.ll
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aix-insert-extract.ll
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aix-internal.ll
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aix-LinkOnceAnyLinkage.ll
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aix-LinkOnceODRLinkage.ll
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aix-llvm-intrinsic.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-lower-block-address.ll
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aix-lower-constant-pool-index.ll
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aix-lower-jump-table-mir.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-lower-jump-table.ll
[NFC] Fix the PowerPC broken cases in D152215.
2023-09-01 02:07:48 -04:00
aix-lr.ll
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aix-nest-param.ll
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aix-nonzero-zerofill.ll
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aix-overflow-toc.py
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aix-p8vector-liveins.ll
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aix-p9-insert-extract.ll
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aix-p9-xxinsertw-xxextractuw.ll
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aix-personality-alias.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-prefixed-instruction-boundary.mir
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aix-print-pc.mir
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aix-readonly-with-relocation.ll
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aix-reference-func-addr-const.ll
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aix-relativeref.ll
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aix-relro-section.ll
[AIX] Handle ReadOnlyWithRel kind on AIX.
2023-08-28 00:21:09 -04:00
aix-return55.ll
[XCOFF] Do not put MergeableCStrings in their own section
2023-07-29 03:24:21 +00:00
aix-rodata-align.ll
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aix-small-local-exec-tls-char.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-small-local-exec-tls-double.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-small-local-exec-tls-float.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-small-local-exec-tls-int.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-small-local-exec-tls-largeaccess.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-small-local-exec-tls-longlong.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-small-local-exec-tls-short.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-space.ll
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aix-sret-param.ll
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aix-static-init-default-priority.ll
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aix-static-init-key-object.ll
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aix-static-init-no-unique-module-id.ll
[AIX] Add threadId and use nanosecond timestamp in sinit/sterm symbols
2023-09-07 17:46:41 +00:00
aix-static-init-non-default-priority.ll
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aix-text-ref.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-text.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-tls-gd-double.ll
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aix-tls-gd-int.ll
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aix-tls-gd-longlong.ll
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aix-tls-gd-target-flags.ll
[PowerPC] Add test to show wrong target flags printed at MO_TLSGDM_FLAG operand. NFC.
2023-09-26 05:13:26 +00:00
aix-tls-ie-ldst.ll
[PowerPC] Support initial-exec TLS relocation on AIX
2023-08-30 16:22:16 +08:00
aix-tls-ie-xcoff-reloc.ll
[PowerPC] Support initial-exec TLS relocation on AIX
2023-08-30 16:22:16 +08:00
aix-tls-le-ldst-double.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-float.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-int.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-longlong.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-ldst-O0.ll
[AIX][TLS] Produce a faster local-exec access sequence with -maix-small-local-exec-tls (And optimize when load/store offsets are 0)
2023-09-07 20:05:29 -05:00
aix-tls-le-xcoff-reloc32.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-xcoff-reloc-large32.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-xcoff-reloc-large.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-le-xcoff-reloc.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-tls-variables-ppc32.ll
…
aix-tls-variables-ppc64.ll
…
aix-tls-xcoff-reloc-large.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-tls-xcoff-reloc.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-tls-xcoff-variables.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-tracetable-csr.ll
…
aix-trampoline.ll
…
aix-undef-func-call.ll
…
aix-user-defined-memcpy.ll
[AIX] Lower some memory intrinsics to millicode functions on AIX
2023-02-20 22:25:49 -05:00
aix-vec_extract_p9_2.ll
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aix-vec_extract_p9.ll
…
aix-vec_insert_elt.ll
[PowerPC][TLS] Add additional TLS X-Form loads/store instructions
2023-06-27 11:33:38 -05:00
aix-vec-arg-spills-callee.ll
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aix-vec-arg-spills-mir.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-vec-arg-spills.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-vector-stack-caller.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-vector-stack.ll
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aix-vector-vararg-caller.ll
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aix-vector-vararg-fixed-caller.ll
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aix-vsx-splatimm.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
aix-weak-reloc.ll
[XCOFF] Force recording a relocation for weak symbol label.
2023-07-05 01:58:18 -04:00
aix-weak-undef-func-call.ll
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aix-weak.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-WeakODRLinkage.ll
…
aix-xcoff-cold.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-xcoff-data-only-notoc.ll
…
aix-xcoff-data-sections.ll
[XCOFF] Do not put MergeableCStrings in their own section
2023-07-29 03:24:21 +00:00
aix-xcoff-data.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-xcoff-endian-error.ll
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aix-xcoff-error-explicit-data-section.ll
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aix-xcoff-exception-section-debug.ll
Revert "[XCOFF][DWARF] XCOFF64 should be able to select the dwarf format in intergrated-as mode."
2023-06-05 02:50:47 -04:00
aix-xcoff-exception-section.ll
…
aix-xcoff-explicit-section.ll
…
aix-xcoff-externL.ll
…
aix-xcoff-funcsect.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-xcoff-huge-relocs.ll
…
aix-xcoff-lcomm.ll
…
aix-xcoff-lower-comm.ll
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aix-xcoff-mergeable-const.ll
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aix-xcoff-mergeable-str.ll
[PowerPC] Add a pass to merge all of the constant global arrays into one pool.
2023-09-07 11:14:56 -04:00
aix-xcoff-reloc-large.ll
…
aix-xcoff-reloc-symb.mir
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-xcoff-reloc.ll
[XCOFF] Write source language ID and CPU version ID into C_FILE symbol.
2023-07-24 00:35:24 -04:00
aix-xcoff-rodata.ll
[PowerPC] Add a pass to merge all of the constant global arrays into one pool.
2023-09-07 11:14:56 -04:00
aix-xcoff-roptr.ll
[AIX][CodeGen] Renaming mroptr to xcoff-mroptr
2023-03-31 10:09:48 -04:00
aix-xcoff-symbol-rename.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
aix-xcoff-textdisassembly.ll
…
aix-xcoff-tls-rename.ll
…
aix-xcoff-toc.ll
…
aix-xcoff-used.ll
…
aix-xcoff-visibility.ll
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alias.ll
…
align.ll
…
alignlongjumptest.mir
…
all-atomics.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
alloca-crspill.ll
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allocate-r0.ll
…
altivec-ord.ll
…
and_add.ll
…
and_sext.ll
…
and_sra.ll
…
and-branch.ll
…
and-elim.ll
…
and-extend-combine.ll
[PowerPC] Use zext instead of anyext in custom and combine (#68784)
2023-10-12 09:32:17 +02:00
and-imm.ll
…
and-mask.ll
…
andc.ll
…
anon_aggr.ll
…
anyext_srl.ll
…
arg_promotion.ll
[IR] Change shufflevector undef mask to poison
2023-04-27 14:41:10 +01:00
arr-fp-arg-no-copy.ll
…
ashr-neg1.ll
…
asm-constraints.ll
…
asm-dialect.ll
…
asm-printer-topological-order.ll
…
asm-template-I.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
asm-Zy.ll
…
asym-regclass-copy.ll
…
atomic-1.ll
…
atomic-2.ll
…
atomic-float.ll
…
atomic-minmax.ll
[PowerPC] Update incr after resetting the register in MI
2023-04-14 17:36:30 +08:00
atomicrmw-uinc-udec-wrap.ll
[LICM] Don't duplicate instructions just because they're free
2023-04-28 14:31:23 +02:00
Atomics-64.ll
…
atomics-constant.ll
…
atomics-fences.ll
…
atomics-i8-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i16-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i32-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i64-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i128-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics-i128.ll
[PowerPC][Atomics] Remove redundant block to clear reservation (#68430)
2023-10-13 10:59:27 +08:00
atomics-indexed.ll
…
atomics-regression.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
atomics.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
available-externally.ll
…
basic-toc-data-def.ll
…
basic-toc-data-extern.ll
…
basic-toc-data-local-linkage.ll
…
bcd-intrinsics.ll
…
bdzlr.ll
…
bfloat16-outer-product.ll
…
big-endian-actual-args.ll
…
big-endian-call-result.ll
…
big-endian-formal-args.ll
…
big-endian-store-forward.ll
…
bitcast-peephole.mir
…
bitcasts-direct-move.ll
…
bitfieldinsert.ll
…
block-placement-1.mir
…
block-placement.mir
…
blockaddress.ll
…
bool-math.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
BoolRetToIntTest-2.ll
…
BoolRetToIntTest.ll
…
botheightreduce.mir
…
bperm.ll
…
branch_coalesce.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
branch_coalescing.mir
PPCBranchCoalescing: Fix invalid branch weights (#67211)
2023-09-25 10:41:04 -07:00
branch_selector.ll
…
branch-hint.ll
…
branch-on-store-cond.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
branch-opt.ll
…
brcond.ll
…
BreakableToken-reduced.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
bswap64.ll
…
bswap-load-store.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
build-vector-allones.ll
…
build-vector-tests.ll
[PowerPC] Optimize VPERM and fix code order for swapping vector operands on LE
2023-09-13 15:00:49 -05:00
build-vector-to-ld-chain.ll
…
buildvec_canonicalize.ll
…
builtins-ppc-elf2-abi.ll
…
builtins-ppc-p8vector.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
builtins-ppc-p9-darn.ll
…
builtins-ppc-p9-f128.ll
…
builtins-ppc-p10permute.ll
…
builtins-ppc-p10vsx.ll
[PowerPC] Update InputOps of Power10 SchedModel
2023-07-07 22:46:22 +08:00
builtins-ppc-xlcompat-check-ldarx-opt.ll
…
builtins-ppc-xlcompat-cmpb-32.ll
…
builtins-ppc-xlcompat-cmpb-64.ll
…
builtins-ppc-xlcompat-compare-64bit-only.ll
…
builtins-ppc-xlcompat-compare.ll
…
builtins-ppc-xlcompat-conversionfunc.ll
…
builtins-ppc-xlcompat-fnabs.ll
…
builtins-ppc-xlcompat-fp.ll
…
builtins-ppc-xlcompat-load-store-reversed-64bit-only.ll
…
builtins-ppc-xlcompat-load-store-reversed.ll
…
builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
…
builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
…
builtins-ppc-xlcompat-math.ll
…
builtins-ppc-xlcompat-maxmin.ll
…
builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
…
builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
…
builtins-ppc-xlcompat-move-tofrom-regs.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
builtins-ppc-xlcompat-msync.ll
…
builtins-ppc-xlcompat-multiply-64bit-only.ll
…
builtins-ppc-xlcompat-multiply.ll
…
builtins-ppc-xlcompat-popcnt.ll
…
builtins-ppc-xlcompat-prefetch.ll
…
builtins-ppc-xlcompat-pwr9-64bit.ll
…
builtins-ppc-xlcompat-pwr9.ll
…
builtins-ppc-xlcompat-stfiw.ll
…
builtins-ppc-xlcompat-sync-32.ll
…
builtins-ppc-xlcompat-sync-64.ll
…
builtins-ppc-xlcompat-test.ll
…
builtins-ppc-xlcompat-trap-64bit-only.ll
…
builtins-ppc-xlcompat-trap-annotations-td.ll
…
builtins-ppc-xlcompat-trap-annotations-tw.ll
…
builtins-ppc-xlcompat-trap.ll
…
bv-pres-v8i1.ll
…
bv-widen-undef.ll
…
byval-agg-info.ll
…
byval-aliased.ll
…
byval-lhs.ll
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
byval.ll
…
callbr-asm-outputs-indirect-isel.ll
[llvm][test] enable/disable -verify-machineinstrs where possible for callbr
2023-02-16 20:28:18 -08:00
calls.ll
…
can-lower-ret.ll
…
cannonicalize-vector-shifts.ll
…
canonical-merge-shuffles.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
cc.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
cfence-double.ll
[llvm] Remove explicit -opaque-pointers flag from tests (NFC)
2023-07-12 14:35:55 +02:00
cfence-float.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
cfence-i128.ll
…
cgp-select.ll
…
change-no-infs.ll
…
check-aix-small-local-exec-tls-opt-IRattribute.ll
[AIX][TLS] Add target attribute for -maix-small-local-exec-tls option.
2023-09-07 20:05:29 -05:00
check-aix-small-local-exec-tls-opt.ll
[AIX][TLS] Add target attribute for -maix-small-local-exec-tls option.
2023-09-07 20:05:29 -05:00
check-cpu.ll
…
cmp_elimination.ll
[PPCMIPeephole] Fix incorrect compare elimination
2023-04-24 10:02:06 -07:00
cmp-cmp.ll
…
cmpb-ppc32.ll
…
cmpb.ll
…
coalesce-ext.ll
…
code-align.ll
…
codemodel.ll
…
coldcc2.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
coldcc.ll
…
collapse-rotates.mir
…
combine_ext_trunc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
combine-fneg.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
combine-setcc.ll
…
combine-sext-and-shl-after-isel.ll
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
combine-to-mulh-shift-amount.ll
…
combine-to-pre-index-store-crash.ll
…
common-chain-aix32.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
common-chain.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
compare-duplicate.ll
…
compare-simm.ll
…
CompareEliminationSpillIssue.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
complex-return.ll
…
compute-regpressure.ll
…
const-nonsplat-array-init.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
const-splat-array-init.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
constant-combines.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
constant-pool.ll
…
constants-i64.ll
[PowerPC] Try to use less instructions to materialize 64-bit constant when High32=Low32.
2023-09-07 13:03:17 -04:00
constants.ll
…
convert-ri-addi-to-ri.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
convert-rr-to-ri-instr-add.mir
…
convert-rr-to-ri-instrs-kill-flag.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
convert-rr-to-ri-instrs-out-of-range.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
convert-rr-to-ri-instrs-R0-special-handling.mir
…
convert-rr-to-ri-instrs.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
convert-rr-to-ri-p9-vector.mir
…
copysignl.ll
…
cr1eq-no-extra-moves.ll
…
cr1eq.ll
…
cr_spilling.ll
…
cr-spills.ll
…
crash.ll
…
crbit-asm-disabled.ll
…
crbit-asm.ll
[PowerPC] Auto gen test checks for #69299. NFC.
2023-10-18 02:21:22 +00:00
crbits.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
crsave.ll
…
crypto_bifs_be.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
crypto_bifs.ll
…
cse-despite-rounding-mode.ll
…
CSR-fit.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
csr-save-restore-order.ll
…
csr-split.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
ctr-cleanup.ll
…
ctr-loop-tls-const.ll
…
ctr-minmaxnum.ll
…
ctrloop-asm.ll
…
ctrloop-constrained-fp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ctrloop-cpsgn.ll
…
ctrloop-do-not-duplicate-mi.mir
…
ctrloop-fp64.ll
…
ctrloop-fp128.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ctrloop-i64.ll
…
ctrloop-i128.ll
…
ctrloop-intrin.ll
…
ctrloop-large-ec.ll
…
ctrloop-le.ll
…
ctrloop-lt.ll
…
ctrloop-ne.ll
…
ctrloop-reg.ll
…
ctrloop-s000.ll
…
ctrloop-sh.ll
…
ctrloop-shortLoops.ll
…
ctrloop-sums.ll
…
ctrloop-udivti3.ll
…
ctrloops32.mir
…
ctrloops64.mir
…
ctrloops-hot-exit.ll
…
ctrloops-pseudo.ll
…
ctrloops-softfloat.ll
…
ctrloops.ll
…
cttz.ll
…
cvt_i64_to_fp.ll
…
cxx_tlscc64.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
darwin-labels.ll
…
dbg.ll
…
DbgValueOtherTargets.test
…
dcbf-p10.ll
…
dcbf.ll
…
dcbt-sched.ll
…
dcbt.ll
…
debug-label-fast-isel.ll
…
debuginfo-split-int.ll
…
debuginfo-stackarg.ll
…
delete-node.ll
…
dform-adjust.ll
…
dform-pair-load-store.ll
…
direct-move-profit.ll
…
disable-ctr-ppcf128.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
DisableHoistingDueToBlockHotnessNoProfileData.mir
…
DisableHoistingDueToBlockHotnessProfileData.mir
…
div-2.ll
…
div-e-32.ll
…
div-e-all.ll
…
dscr-set.ll
…
dsolocal-pic.ll
…
dsolocal-static.ll
…
dssall.ll
…
duplicate-returns-for-tailcall.ll
…
dyn-alloca-aligned.ll
…
dyn-alloca-offset.ll
…
e500-1.ll
…
early-ret2.ll
…
early-ret-verify.mir
…
early-ret.ll
…
early-ret.mir
…
ec-input.ll
…
eh-dwarf-cfa.ll
…
eieio.ll
…
elf64-byval-cc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
elf-common.ll
…
eliminate-compare-of-copy.ll
…
empty-functions.ll
…
emptystruct.ll
…
emutls_generic.ll
…
eqv-andc-orc-nor.ll
…
exp10-libcall.ll
IR: Add llvm.exp10 intrinsic
2023-09-01 19:45:03 -04:00
expand-contiguous-isel.ll
RegisterCoalescer: Fix name of pass
2023-06-21 10:30:43 -04:00
expand-foldable-isel.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
expand-isel-1.mir
…
expand-isel-2.mir
…
expand-isel-3.mir
…
expand-isel-4.mir
…
expand-isel-5.mir
…
expand-isel-6.mir
…
expand-isel-7.mir
…
expand-isel-8.mir
…
expand-isel-9.mir
…
expand-isel-10.mir
…
expand-isel-liveness.mir
…
expand-isel.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ext-bool-trunc-repl.ll
[ConstExpr] Remove select constant expression
2023-03-16 10:32:08 +01:00
extra-toc-reg-deps.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
extract-and-store.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
extsh.ll
…
extswsli.ll
…
f32-to-i64.ll
…
f128_ldst.ll
…
f128-aggregates.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-arith.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-bitcast.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-branch-cond.ll
…
f128-compare.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-conv.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-fma.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-passByValue.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-rounding.ll
…
f128-truncateNconv.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
f128-vecExtractNconv.ll
…
fabs.ll
DAG: Remove hasBitPreservingFPLogic
2023-02-14 10:25:24 -04:00
fast-isel-binary.ll
…
fast-isel-br-const.ll
…
fast-isel-branch.ll
…
fast-isel-call.ll
…
fast-isel-cmp-imm.ll
…
fast-isel-const.ll
…
fast-isel-conversion-p5.ll
…
fast-isel-conversion.ll
…
fast-isel-crash.ll
…
fast-isel-ext.ll
…
fast-isel-fcmp-nan.ll
…
fast-isel-fold.ll
…
fast-isel-fpconv.ll
…
fast-isel-GEP-coalesce.ll
…
fast-isel-i64offset.ll
…
fast-isel-icmp-split.ll
…
fast-isel-indirectbr.ll
…
fast-isel-load-store-vsx.ll
…
fast-isel-load-store.ll
…
fast-isel-pcrel.ll
…
fast-isel-redefinition.ll
…
fast-isel-ret.ll
…
fast-isel-rsp.ll
…
fast-isel-shifter.ll
…
fastcc_stacksize.ll
…
fastisel-gep-promote-before-add.ll
…
fcpsgn.ll
…
fdiv-combine.ll
…
fdiv.ll
…
fixup-kill-dead-flag-crash.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
float-asmprint.ll
…
float-load-store-pair.ll
…
float-logic-ops.ll
…
float-to-int.ll
…
float-vector-gather.ll
…
floatPSA.ll
…
flt-preinc.ll
…
fma-aggr-FMF.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fma-assoc.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
fma-combine.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fma-ext.ll
…
fma-mutate-duplicate-vreg.ll
…
fma-mutate-register-constraint.ll
…
fma-mutate.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
fma-negate.ll
…
fma-precision.ll
…
fma.ll
…
fmaxnum.ll
…
fmf-propagation.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fminnum.ll
…
fnabs.ll
…
fneg.ll
…
fold_swtest_br.ll
…
fold-frame-offset-using-rr.mir
…
fold-li.ll
…
fold-remove-li.ll
…
fold-rlwinm-1.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fold-rlwinm.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
fold-rot-and-peephole.mir
Reland https://reviews.llvm.org/D159073.
2023-09-26 06:24:47 -04:00
fold-zero.ll
…
fp2int2fp-ppcfp128.ll
…
fp64-to-int16.ll
…
fp128-bitcast-after-operation.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
fp128-libcalls.ll
…
fp_to_uint.ll
…
fp-branch.ll
…
fp-classify.ll
Pre-commit some PowerPC test cases
2023-09-28 15:51:14 +08:00
fp-int128-fp-combine.ll
…
fp-int-conversions-direct-moves.ll
…
fp-int-fp.ll
…
fp-intrinsics-fptosi-legal.ll
…
fp-splat.ll
…
fp-strict-conv-f128.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-strict-conv-spe.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
fp-strict-conv.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-strict-f128.ll
…
fp-strict-fcmp-noopt.ll
…
fp-strict-fcmp-spe.ll
…
fp-strict-fcmp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-strict-minmax.ll
…
fp-strict-round.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-strict.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fp-to-int-ext.ll
…
fp-to-int-to-fp.ll
…
fpcopy.ll
…
fpscr-intrinsics.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
fptoui-be-crash.ll
[PowerPC] Do not attempt to combine fptoui without FPCVT
2023-05-24 11:14:26 -05:00
frame_index_scavenging.mir
…
frame-size.ll
…
frameaddr.ll
…
Frames-dyn-alloca-with-func-call.ll
…
Frames-dyn-alloca.ll
…
Frames-large.ll
…
Frames-leaf.ll
…
Frames-small.ll
…
Frames-stack-floor.ll
…
frem.ll
…
frounds.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fsel.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
fsl-e500mc.ll
…
fsl-e5500.ll
…
fsqrt.ll
…
fsub-fneg.ll
…
ftrunc-legalize.ll
…
ftrunc-vec.ll
…
func-addr-consts.ll
…
func-addr.ll
…
func-alias.ll
…
funnel-shift-rot.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
funnel-shift.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
fusion-load-store.ll
…
future-check-features.ll
…
glob-comp-aa-crash.ll
…
global-address-non-got-indirect-access.ll
[SDAG] Don't transfer !range metadata without !noundef to SDAG (PR64589)
2023-08-14 09:04:27 +02:00
gnu-attribute.ll
…
gpr-vsr-spill.ll
…
handle-f16-storage-type.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
hardware-loops-crash.ll
…
hello.ll
…
hidden-vis-2.ll
…
hidden-vis.ll
…
hoist-logic.ll
…
htm-ttest.ll
…
htm.ll
…
huge-frame-call.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
huge-frame-size.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
huge-frame-unsupported.ll
…
i1-ext-fold.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
i1-to-double.ll
…
i32-to-float.ll
…
i64_fp_round.ll
…
i64_fp.ll
…
i64-to-float.ll
…
i128-and-beyond.ll
…
ia-mem-r0.ll
…
ia-neg-const.ll
…
iabs.ll
…
idiv_large.ll
[CodeGen] Always expand division larger than i128
2023-03-01 15:33:45 +01:00
ifcvt_cr_field.ll
…
ifcvt-diamond-ret.mir
…
ifcvt-forked-bug-2016-08-08.ll
…
ifcvt.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ifcvt.mir
…
ifunc.ll
…
illegal-element-type.ll
…
in-asm-f64-reg.ll
…
inc-of-add.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
indexed-load.ll
…
indirect-hidden.ll
…
indirectbr.ll
…
inline-asm-clobber-warning.ll
…
inline-asm-dollarpc.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-label.ll
…
inline-asm-multilevel-gep.ll
…
inline-asm-physical-fpr-spe.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
inline-asm-physical-fpr.ll
…
inline-asm-s-modifier.ll
…
inline-asm-scalar-to-vector-error.ll
…
inline-asm-vsx-clobbers.ll
…
inlineasm-copy.ll
…
inlineasm-extendedmne.ll
…
inlineasm-i64-reg.ll
…
inlineasm-output-template.ll
…
inlineasm-vsx-reg.ll
…
instr-properties.ll
…
instruction-mix-remarks-BCTRL_LWZinto_toc.ll
…
int128_ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
int-fp-conv-0.ll
…
int-fp-conv-1.ll
…
inverted-bool-compares.ll
…
is_fpclass.ll
[FPEnv][PowerPC] Correct strictfp tests.
2023-07-26 09:12:29 -04:00
isel-rc-nox0.ll
…
isel.ll
…
ispositive.ll
…
issue55983.ll
[llvm] Remove explicit -opaque-pointers flag from tests (NFC)
2023-07-12 14:35:55 +02:00
isync.ll
…
itofp128.ll
…
jaggedstructs.ll
…
jump-table.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
jump-tables-collapse-rotate-remove-SrcMI.mir
…
jump-tables-collapse-rotate.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
kernel-fp-round.ll
…
kill_flag_verification.ll
[PowerPC] Fix missing kill flag update for XVCVDPSP transformations (#67997)
2023-10-06 10:24:54 -04:00
knowCRBitSpill.ll
…
LargeAbsoluteAddr.ll
…
larger-than-red-zone.ll
…
lbz-from-ld-shift.ll
…
lbzux.ll
…
ld-bswap64-no-ldbrx.ll
…
ld-st-upd.ll
…
ldexp-libcall.ll
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
ldexp.ll
[DAG] Unroll and expand illegal result of LDEXP and POWI instead of widen.
2023-06-21 14:27:39 +08:00
ldst-16-byte-asm.mir
…
ldst-16-byte.mir
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
ldst-align.ll
…
ldtoc-inv.ll
…
legalize-invert-br_cc.ll
…
legalize-vaarg.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
lha.ll
…
licm-remat.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
licm-tocReg.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
livephysregs.mir
…
livevars-crash1.mir
…
livevars-crash2.mir
…
llrint-conv.ll
…
llround-conv.ll
…
llvm.frexp.ll
IR: Add llvm.frexp intrinsic
2023-06-28 14:50:16 -04:00
load-and-splat.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
load-constant-addr.ll
…
load-rightmost-vector-elt.ll
…
load-shift-combine.ll
…
load-shuffle-and-shuffle-store.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
load-two-flts.ll
…
load-v4i8-improved.ll
…
logic-ops-on-compares.ll
…
long-compare.ll
…
longcall.ll
[PowerPC] Bail out of FISel when lowering long calls
2023-02-16 16:15:32 -05:00
longdbl-truncate.ll
…
longdouble-pack.ll
…
loop-align.ll
…
loop-comment.ll
…
loop-data-prefetch-inner.ll
…
loop-data-prefetch.ll
…
loop-hoist-toc-save.ll
…
loop-instr-form-non-inc.ll
[PowerPC] Adjust tests after e351b9b66d.
2023-05-12 20:20:13 +01:00
loop-instr-form-prepare.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
loop-instr-prep-non-const-increasement.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
loop-p10-pair-prepare.ll
…
loop-prep-all.ll
…
lower-globaladdr32-aix-asm.ll
…
lower-globaladdr32-aix.ll
RegisterCoalescer: Fix name of pass
2023-06-21 10:30:43 -04:00
lower-globaladdr64-aix-asm.ll
…
lower-globaladdr64-aix.ll
RegisterCoalescer: Fix name of pass
2023-06-21 10:30:43 -04:00
lower-intrinsics-afn-mass_notail.ll
…
lower-intrinsics-afn-mass.ll
…
lower-intrinsics-fast-mass_notail.ll
…
lower-intrinsics-fast-mass.ll
…
lower-intrinsics-nofast-mass.ll
…
lower-massv-attr.ll
…
lower-massv.ll
…
lower-scalar-mass-afn.ll
…
lower-scalar-mass-fast.ll
…
lower-scalar-mass-nofast.ll
…
LQ-STQ-32bit-offset.ll
…
LQ-STQ.ll
…
lrint-conv.ll
…
lround-conv.ll
…
lsa.ll
…
lsr-ctrloop.ll
…
lsr-insns-cost.ll
…
lsr-postinc-pos.ll
[SCEVExpander] Always use scevgep as name
2023-03-17 14:27:03 +01:00
lsr-profitable-chain.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
lxv-aligned-stack-slots.ll
…
lxvw4x-bug.ll
…
machine-backward-cp.mir
…
machine-combiner.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
machine-cse-rm-pre.mir
…
machine-pre.ll
…
machinelicm-cse-dead-flag.mir
…
macro-fusion.ll
…
macro-fusion.mir
…
maddld.ll
…
mask64.ll
…
mature-mc-support.ll
…
mc-instrlat.ll
…
mcm-1.ll
…
mcm-2.ll
…
mcm-3.ll
…
mcm-4.ll
…
mcm-5.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
mcm-6.ll
…
mcm-7.ll
…
mcm-8.ll
…
mcm-9.ll
…
mcm-10.ll
…
mcm-11.ll
…
mcm-12.ll
…
mcm-13.ll
…
mcm-default.ll
…
mcm-obj-2.ll
…
mcm-obj.ll
…
mcount-insertion.ll
…
mcp-elim-eviction-chain.mir
…
MCSE-caller-preserved-reg.ll
…
mem_update.ll
…
mem-rr-addr-mode.ll
…
memcmp-mergeexpand.ll
…
memcmp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
memcmpIR.ll
…
memCmpUsedInZeroEqualityComparison.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
memcpy_dereferenceable.ll
…
memcpy-vec.ll
…
memset-nc-le.ll
…
memset-tail.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
merge_stores_dereferenceable.ll
…
merge-st-chain-op.ll
…
mergeable-string-pool-large.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
mergeable-string-pool-pass-only.mir
[PowerPC] Add a pass to merge all of the constant global arrays into one pool.
2023-09-07 11:14:56 -04:00
mergeable-string-pool.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
MergeConsecutiveStores.ll
…
mflr-store.mir
…
mftb.ll
…
mi-peephole-splat.ll
…
mi-peephole.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
mi-peepholes-trap-opt.mir
…
mi-scheduling-lhs.ll
…
mi-simplify-code.mir
…
misched-inorder-latency.ll
…
misched.ll
…
mma-acc-copy-hints.ll
…
mma-acc-memops.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
mma-acc-spill.ll
…
mma-integer-based-outer-product.ll
…
mma-intrinsics.ll
…
mma-outer-product.ll
…
mma-phi-accs.ll
…
mmaplus-acc-spill.ll
…
mmaplus-intrinsics.ll
[PowerPC][Future] Enable __builtin_mma_xxm[t|f]acc
2023-07-14 13:38:40 -05:00
MMO-flags-assertion.ll
…
more-dq-form-prepare.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
mtvsrc-mfvscr-PPCVSXSwapRemoval.ll
…
mtvsrdd.ll
…
mul-const-i64.ll
…
mul-const-vector.ll
[PowerPC] remove XXSWAPD after load from CP which is a splat value
2023-02-16 19:21:35 -05:00
mul-const.ll
…
mul-high.ll
…
mul-with-overflow.ll
…
mulhs.ll
…
mulld.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
mulli.ll
…
mult-alt-generic-powerpc64.ll
…
mult-alt-generic-powerpc.ll
…
multi-return.ll
…
named-reg-alloc-r0.ll
…
named-reg-alloc-r1-64.ll
…
named-reg-alloc-r1.ll
…
named-reg-alloc-r2-64.ll
…
named-reg-alloc-r2.ll
…
named-reg-alloc-r13-64.ll
…
named-reg-alloc-r13.ll
…
neg-abs.ll
…
neg.ll
…
negate-i1.ll
…
negctr.ll
…
no-ctr-loop-if-exit-in-nested-loop.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
no-dead-strip.ll
…
no-dup-of-bdnz.ll
…
no-dup-spill-fp.ll
…
no-duplicate.ll
…
no-ext-with-count-zeros.ll
…
no-extra-fp-conv-ldst.ll
…
no-misaligned-tocl.ll
…
no-pref-jumps.ll
…
no-rlwimi-trivial-commute.mir
…
NoCRFieldRedefWhenSpillingCRBIT.mir
…
nofpexcept.ll
[FPEnv][PowerPC] Correct strictfp tests.
2023-07-26 09:12:29 -04:00
nomerge.ll
[NFC] Update CodeGen/*/nomerge.ll tests with utils/update_llc_test_checks.py.
2023-04-03 19:52:39 -04:00
non-debug-mi-search-frspxsrsp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
non-simple-args-intrin.ll
…
noPermuteFormasking.ll
…
not-fixed-frame-object.ll
…
novrsave.ll
…
O0-pipeline.ll
[llvm] add CallBrPrepare pass to pipelines
2023-02-16 17:58:34 -08:00
O3-pipeline.ll
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
opt-builtins-ppc-xlcompat-cas.ll
…
opt-cmp-inst-cr0-live.ll
…
opt-cmp-rec-postra.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
opt-li-add-to-addi.ll
…
opt-sub-inst-cr0-live.mir
…
optcmp.ll
…
optimize-andiso.ll
…
optimize-vector.ll
[PowerPC] Improve code gen for vector add
2023-07-13 15:21:49 -04:00
optnone-crbits-i1-ret.ll
…
or-addressing-mode.ll
…
ori_imm32.ll
…
ori_imm64.ll
…
out-of-range-dform.ll
…
overflow-intrinsic-optimizations.ll
…
p8-isel-sched.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
p8-scalar_vector_conversions.ll
Reland https://reviews.llvm.org/D159073.
2023-09-26 06:24:47 -04:00
p8altivec-shuffles-pred.ll
…
p9_copy_fp.ll
…
p9-dform-load-alignment.ll
…
p9-vbpermd.ll
…
p9-vector-compares-and-counts.ll
…
p9-vector-sign-extend.ll
…
p9-vinsert-vextract.ll
…
p9-xxinsertw-xxextractuw.ll
…
p10-bit-manip-ops.ll
…
p10-bswap.ll
…
p10-check-features.ll
…
p10-constants.ll
…
p10-fi-elim.ll
…
p10-handle-split-promote-vec.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
p10-setbc-ri.ll
…
p10-setbc-rr.ll
…
p10-setbcr-ri.ll
…
p10-setbcr-rr.ll
…
p10-setboolean-ext-fp.ll
…
p10-setnbc-ri.ll
…
p10-setnbc-rr.ll
…
p10-setnbcr-ri.ll
…
p10-setnbcr-rr.ll
…
p10-spill-creq.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
p10-spill-crgt.ll
[DAG] FoldSetCC - add missing icmp(X,undef) -> isTrueWhenEqual case (REAPPLIED)
2023-09-13 12:33:39 +01:00
p10-spill-crlt.ll
…
p10-spill-crun.ll
…
p10-splatImm32-undef.ll
…
p10-splatImm32.ll
…
p10-splatImm-CPload-pcrel.ll
…
p10-splatImm.ll
…
p10-string-ops.ll
…
p10-vector-divide.ll
…
p10-vector-mask-ops.ll
…
p10-vector-modulo.ll
…
p10-vector-multiply.ll
…
p10-vector-rotate.ll
…
p10-vector-shift.ll
…
p10-vector-sign-extend.ll
…
p10-vsx-pcv.ll
…
P10-stack-alignment.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
paired-vector-intrinsics.ll
…
pcrel_ldst.ll
…
pcrel-block-address.ll
…
pcrel-byte-loads.ll
…
pcrel-call-linkage-leaf.ll
…
pcrel-call-linkage-simple.ll
…
pcrel-call-linkage-with-calls.ll
…
pcrel-got-indirect.ll
…
pcrel-indirect-call.ll
…
pcrel-jump-table.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
pcrel-linkeropt-option.ll
…
pcrel-linkeropt.ll
…
pcrel-local-caller-toc.ll
…
pcrel-relocation-plus-offset.ll
…
pcrel-tail-calls.ll
…
pcrel-tls_get_addr_clobbers.ll
…
pcrel-tls-general-dynamic.ll
…
pcrel-tls-initial-exec.ll
…
pcrel-tls-local-dynamic.ll
…
pcrel-tls-local-exec.ll
…
pcrel.ll
…
peephole-align.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
peephole-cmp-eq.mir
…
peephole-miscompile-extswsli.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
peephole-phi-acc.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
peephole-subreg-def.mir
…
perfect-shuffle.ll
…
pgo-ref-directive.ll
[XCOFF] Do not generate the special .ref for zero-length sections (#66805)
2023-09-28 01:33:41 -04:00
phi-eliminate.mir
…
pie.ll
…
pip-inner.ll
…
popcnt-zext.ll
…
popcnt.ll
…
popcount.ll
…
post-ra-ec.ll
…
pow_massv_075_025exp.ll
…
pow-025-075-intrinsic-scalar-mass-afn.ll
…
pow-025-075-intrinsic-scalar-mass-fast.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pow-025-075-nointrinsic-scalar-mass-fast.ll
…
pow.75.ll
…
power9-moves-and-splats.ll
…
powf_massv_075_025exp.ll
…
ppc32-align-long-double-sf.ll
…
ppc32-constant-BE-ppcf128.ll
…
ppc32-cyclecounter.ll
…
ppc32-i1-stack-arguments-abi-bug.ll
…
ppc32-i1-vaarg.ll
…
ppc32-i64-to-float-conv.ll
…
ppc32-lshrti3.ll
…
ppc32-nest.ll
…
ppc32-pic-large.ll
…
ppc32-pic.ll
…
ppc32-secure-plt-tls2.ll
…
ppc32-secure-plt-tls.ll
…
ppc32-selectcc-i64.ll
…
ppc32-skip-regs.ll
…
ppc32-vacopy.ll
…
ppc64-32bit-addic.ll
…
ppc64-abi-extend.ll
…
ppc64-acc-regalloc-bugfix.ll
…
ppc64-acc-regalloc.ll
…
ppc64-align-long-double.ll
…
ppc64-altivec-abi.ll
…
ppc64-anyregcc-crash.ll
…
ppc64-anyregcc.ll
…
ppc64-blnop.ll
…
ppc64-byval-align.ll
…
ppc64-byval-larger-struct.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc64-byval-multi-store.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc64-calls.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ppc64-crash.ll
…
ppc64-crsave.mir
…
ppc64-cyclecounter.ll
…
ppc64-elf-abi.ll
[PowerPC] Correctly use ELFv2 ABI on all OS's that use the ELFv2 ABI
2023-02-20 18:11:24 -05:00
ppc64-fastcc-fast-isel.ll
…
ppc64-fastcc.ll
…
ppc64-func-desc-hoist.ll
…
ppc64-gep-opt.ll
…
ppc64-get-cache-line-size.ll
…
ppc64-i128-abi.ll
…
ppc64-icbt-pwr7.ll
[SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (#66601)
2023-09-18 08:58:50 -07:00
ppc64-icbt-pwr8.ll
…
ppc64-inlineasm-clobber.ll
…
ppc64-linux-func-size.ll
…
ppc64-nest.ll
…
ppc64-nonfunc-calls.ll
[AIX][TLS] Produce a faster local-exec access sequence with -maix-small-local-exec-tls (And optimize when load/store offsets are 0)
2023-09-07 20:05:29 -05:00
ppc64-notoc-rm-relocation.ll
…
ppc64-P9-mod.ll
…
ppc64-P9-setb.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc64-P9-vabsd.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
ppc64-patchpoint.ll
…
ppc64-pre-inc-no-extra-phi.ll
…
ppc64-prefetch.ll
…
ppc64-r2-alloc.ll
…
ppc64-rop-protection-aix.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
ppc64-rop-protection.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
ppc64-sibcall-shrinkwrap.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
ppc64-sibcall.ll
…
ppc64-smallarg.ll
…
ppc64-stackmap-nops.ll
…
ppc64-stackmap.ll
…
ppc64-toc.ll
…
ppc64-vaarg-int.ll
…
ppc64-varargs.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc64-xxsplti32dx-pattern-check.ll
…
ppc64-zext.ll
…
ppc64le-aggregates.ll
…
ppc64le-calls.ll
…
ppc64le-crsave.ll
…
ppc64le-localentry-large.ll
…
ppc64le-localentry.ll
…
ppc64le-smallarg.ll
…
ppc440-fp-basic.ll
…
ppc440-msync.ll
…
ppc_fp128-bcwriter.ll
…
ppc-32bit-build-vector.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-32bit-shift.ll
…
ppc-clear-before-return.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-crbits-onoff.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ppc-ctr-dead-code.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-disable-non-volatile-cr.ll
…
ppc-empty-fs.ll
…
ppc-float-spill.ll
…
ppc-label2.ll
…
ppc-label.ll
…
ppc-partword-atomic.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ppc-passname-assert.ll
…
ppc-passname.ll
…
ppc-prologue.ll
…
ppc-redzone-alignment-bug.ll
…
ppc-rotate-clear.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-shrink-wrapping.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppc-shufflevector-combine.ll
…
ppc-TOC-stats.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
ppc-vaarg-agg.ll
…
ppcf128-1-opt.ll
…
ppcf128-1.ll
…
ppcf128-2.ll
…
ppcf128-3.ll
…
ppcf128-4.ll
…
ppcf128-constrained-fp-intrinsics.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
ppcf128-endian.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
ppcf128-freeze.mir
Fix MIR failure after b922a362
2023-09-08 16:33:45 +08:00
ppcf128sf.ll
…
ppcsoftops.ll
Disable call to fma for soft-float
2023-09-28 14:06:54 +05:30
pr3711_widen_bit.ll
…
pr12757.ll
…
pr13641.ll
…
pr13891.ll
…
pr15031.ll
…
pr15359.ll
…
pr15630.ll
…
pr15632.ll
…
pr16556-2.ll
…
pr16556.ll
…
pr16573.ll
…
pr17168.ll
…
pr17354.ll
…
pr18663-2.ll
…
pr18663.ll
…
pr20442.ll
…
pr22711.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
pr24216.ll
…
pr24546.ll
…
pr24636.ll
[ConstExpr] Remove select constant expression
2023-03-16 10:32:08 +01:00
pr25080.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr25157-peephole.ll
…
pr25157.ll
…
pr26180.ll
…
pr26193.ll
…
pr26356.ll
…
pr26378.ll
…
pr26381.ll
…
pr26617.ll
…
pr26690.ll
…
pr27078.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr27350.ll
…
pr28130.ll
…
pr28630.ll
…
pr30451.ll
…
pr30640.ll
…
pr30663.ll
…
pr30715.ll
…
pr31144.ll
…
pr32063.ll
…
pr32140.ll
…
pr33093.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr33547.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr35402.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr35688.ll
…
pr36068.ll
…
pr36292.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr38087.ll
…
pr38899-split-register-at-spill.mir
…
pr39478.ll
…
pr39815.ll
…
pr40922.ll
[NFC] Autogenerate CodeGen/PowerPC/pr40922.ll
2023-06-25 21:05:06 +00:00
pr41088.ll
…
pr41177.ll
…
pr42492.ll
…
pr43527.ll
…
pr43976.ll
…
pr44183.ll
…
pr44239.ll
…
pr45186.ll
…
pr45297.ll
…
pr45301.ll
[PowerPC] Add function pointer alignment to DataLayout
2023-04-18 13:00:27 -04:00
pr45432.ll
…
pr45448.ll
…
pr45628.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr45709.ll
[DAG] FoldSetCC - add missing icmp(X,undef) -> isTrueWhenEqual case (REAPPLIED)
2023-09-13 12:33:39 +01:00
pr46759.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr46923.ll
…
pr47373.ll
[PowerPC] Correctly use ELFv2 ABI on all OS's that use the ELFv2 ABI
2023-02-20 18:11:24 -05:00
pr47660.ll
…
pr47707.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr47830.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr47891.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr47916.ll
…
pr48388.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr48519.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr48527.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr49092.ll
…
pr49509.ll
…
pr52894-32bit.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr52894.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
pr55463.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
pr55857.ll
…
pr55911.ll
…
pr56469.ll
…
pr61315.ll
[PowerPC] Update pr61315.ll to address D146632 failure
2023-04-05 21:24:59 -05:00
pr61882.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
PR3488.ll
…
PR33636.ll
…
PR33671.ll
…
PR35812-neg-cmpxchg.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
pre-inc-disable.ll
[PowerPC] Fix the xxperm swap requirements
2023-04-05 20:13:40 -05:00
prefer-dqform.ll
…
preinc-ld-sel-crash.ll
…
preincprep-i64-check.ll
…
preincprep-invoke.ll
…
preincprep-nontrans-crash.ll
…
private.ll
…
prolog_vec_spills.mir
…
pwr3-6x.ll
…
pwr7-gt-nop.ll
…
pzero-fp-xored.ll
…
quadint-return.ll
…
r31.ll
…
read-set-flm.ll
[PowerPC] Implement builtin for mffsl
2023-09-05 11:22:09 +08:00
recipest.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
reduce_cr.ll
…
reduce_scalarization02.ll
…
reduce_scalarization.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
redundant-copy-after-tail-dup.ll
…
reg_copy.mir
…
reg-coalesce-simple.ll
…
reg-names.ll
…
reg-scavenging.ll
…
regalloc-fast-debug-spill.ll
…
register-pressure-reduction.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
register-pressure.ll
[PowerPC/SPE] powerpcspe load and store instruction has
2023-07-23 13:24:35 +05:30
reloc-align.ll
…
remap-crash.ll
…
remat-imm.ll
…
rematerializable-instruction-machine-licm.ll
…
remove-copy-crunsetcrbit.mir
RegisterCoalescer: Fix name of pass
2023-06-21 10:30:43 -04:00
remove-implicit-use.mir
…
remove-redundant-li-implicit-reg.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
remove-redundant-li-skip-imp-kill.mir
…
remove-redundant-load-imm.ll
…
remove-redundant-load-imm.mir
…
remove-redundant-moves.ll
…
remove-redundant-toc-saves.ll
…
remove-self-copies.mir
…
repeated-fp-divisors.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
resolvefi-basereg.ll
…
resolvefi-disp.ll
…
respect-rounding-mode.ll
…
restore-r30.ll
…
retaddr2.ll
…
retaddr_multi_levels.ll
…
retaddr.ll
…
return-val-i128.ll
…
rldimi.ll
Pre-commit some PowerPC test cases
2023-09-28 15:51:14 +08:00
rlwimi2.ll
…
rlwimi3.ll
…
rlwimi-and-or-bits.ll
…
rlwimi-and.ll
…
rlwimi-commute.ll
…
rlwimi-dyn-and.ll
…
rlwimi-keep-rsh.ll
…
rlwimi.ll
…
rlwinm2.ll
…
rlwinm_rldicl_to_andi.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
rlwinm-zero-ext.ll
…
rlwinm.ll
…
rm-zext.ll
…
rotl-2.ll
…
rotl-64.ll
…
rotl-rotr-crash.ll
…
rotl.ll
…
rounding-ops.ll
…
rounding-rm-flag.ll
…
rs-undef-use.ll
…
s000-alias-misched.ll
…
saddo-ssubo.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
sat-add.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
sat-register-clobber.ll
…
saturating-intrinsics.ll
…
save-bp.ll
…
save-cr-ppc32svr4.ll
…
save-crbp-ppc32svr4.ll
…
scalar_cmp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar_vector_test_1.ll
…
scalar_vector_test_2.ll
…
scalar_vector_test_3.ll
…
scalar_vector_test_4.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar_vector_test_5.ll
…
scalar-double-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-equal.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-float-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-i8-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-i16-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-i32-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-i64-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scalar-min-max-p10.ll
…
scalar-min-max.ll
…
scalar-rounding-ops.ll
…
scalars-in-altivec-regs.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
scavenging.mir
…
sched-addi.ll
…
schedule-addi-load.mir
Fix MIR failure after b922a362
2023-09-08 16:33:45 +08:00
scheduling-mem-dependency.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
sdag-ppcf128.ll
…
sdiv-pow2.ll
…
sections.ll
…
select_const.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
select_lt0.ll
…
select-addrRegRegOnly.ll
…
select-cc.ll
…
select-constant-xor.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
select-i1-vs-i1.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
select-to-branch.mir
…
select.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
selectiondag-extload-computeknownbits.ll
…
selectiondag-sextload.ll
…
set0-v8i16.ll
…
setcc_no_zext.ll
…
setcc-logic.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
setcc-sub-flag.ll
…
setcc-to-sub.ll
Pre-commit some PowerPC test cases
2023-09-28 15:51:14 +08:00
setcc-vector.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
setcclike-or-comb.ll
…
setcr_bc2.mir
…
setcr_bc3.mir
…
setcr_bc.mir
…
seteq-0.ll
…
setrnd.ll
…
sext_elimination.mir
[PowerPC] Improve kill flag computation and add verification after MI peephole
2023-09-22 15:26:39 -04:00
sext-vector-inreg.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
sh-overflow.mir
…
shift128.ll
…
shift_mask.ll
…
shift-cmp.ll
…
shl_elim.ll
…
shl_sext.ll
…
shrink-wrap.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
shrink-wrap.mir
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
sign_ext_inreg1.ll
…
sign-ext-atomics.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
signbit-shift.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
simplifyConstCmpToISEL.ll
…
sink-down-more-instructions-1.mir
…
sink-down-more-instructions-regpressure-high.mir
…
sink-side-effect.ll
[CGP] Remove dead PHI nodes before elimination of mostly empty blocks
2023-08-29 04:35:06 +00:00
sj-ctr-loop.ll
…
sjlj_no0x.ll
…
sjlj.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
small-arguments.ll
…
sms-cpy-1.ll
Ignore load/store until stack address computation
2023-06-26 13:50:36 -07:00
sms-grp-order.ll
…
sms-iterator.ll
[CGP] Remove dead PHI nodes before elimination of mostly empty blocks
2023-08-29 04:35:06 +00:00
sms-large-stages.mir
…
sms-phi-1.ll
…
sms-phi-2.ll
…
sms-phi-3.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
sms-phi-5.ll
…
sms-phi.ll
…
sms-remark.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
sms-simple.ll
…
smulfixsat.ll
…
spe-fastmath.ll
…
spe-hwdouble.ll
…
spe.ll
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
2023-06-21 10:24:40 +00:00
spill_p9_setb.ll
…
spill-nor0.ll
…
spill-nor0.mir
…
spill-vec-pair.ll
…
splat-bug.ll
…
splat-larger-types-as-v16i8.ll
…
split-index-tc.ll
…
splitstore-check-volatile.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
srem-vector-lkk.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
srl-mask.ll
…
stack_pointer_vec_spills.mir
…
stack-clash-dynamic-alloca.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
stack-clash-prologue-nounwind.ll
…
stack-clash-prologue.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
stack-coloring-vararg.mir
…
stack-guard-oob.ll
[IR] Make stack protector symbol dso_local according to -f[no-]direct-access-external-data
2023-05-23 09:49:57 -07:00
stack-guard-reassign.ll
…
stack-no-redzone.ll
…
stack-protector.ll
…
stack-realign.ll
…
stack-restore-with-setjmp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
stackmap-frame-setup.ll
…
stacksize.ll
…
std-unal-fi.ll
…
stdux-constuse.ll
…
stfiwx-2.ll
…
stfiwx.ll
…
store_fptoi.ll
Reland "[PowerPC] Simplify fp-to-int store optimization"
2023-06-05 13:53:08 +08:00
store-combine.ll
…
store-constant.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
store-forward-be32.ll
…
store-forward-be64.ll
…
store-load-fwd.ll
…
store-rightmost-vector-elt.ll
…
store-update.ll
…
structsinmem.ll
…
structsinregs.ll
…
stubs.ll
…
stwu8.ll
…
stwu-gta.ll
…
stwu-sched.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
stwux.ll
…
sub-bv-types.ll
…
sub-of-not.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
subc.ll
…
subreg-killed.mir
…
subreg-postra-2.ll
…
subreg-postra.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
subtract_from_imm.ll
…
svr4-redzone.ll
…
swap-reduction.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-1.ll
…
swaps-le-2.ll
…
swaps-le-3.ll
…
swaps-le-4.ll
…
swaps-le-5.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-6.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-7.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
swaps-le-8.ll
…
tail-dup-analyzable-fallthrough.ll
…
tail-dup-branch-to-fallthrough.ll
…
tail-dup-break-cfg.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
tail-dup-layout.ll
…
tailcall1-64.ll
…
tailcall1.ll
…
tailcall-speculatable-callee.ll
…
tailcall-string-rvo.ll
…
tailcallpic1.ll
…
test_call_aix.ll
…
test_func_desc.ll
Use empty symbol name for XCOFF text csect
2023-07-15 16:13:48 -04:00
test-and-cmp-folding.ll
…
test-vector-insert.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
testBitReverse.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesi32gtu.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesi32leu.ll
…
testComparesi32ltu.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesieqss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiequs.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigess.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigeus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesigtus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesilesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesilesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesilesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiless.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesileus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiltus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesinesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesinesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesinesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesiness.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesineus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqsc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqsi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslleqss.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllequs.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgess.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgeus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllgtus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslllesc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslllesi.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testCompareslllesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllless.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllleus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltsll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltuc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltui.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllltus.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllnesll.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
testComparesllneull.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
thread-pointer.ll
…
tls_get_addr_clobbers.ll
…
tls_get_addr_fence1.mir
…
tls_get_addr_fence2.mir
…
tls_get_addr_stackframe.ll
…
tls-crash.mir
…
tls-cse.ll
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
tls-debug-aix.ll
…
tls-pic.ll
…
tls-pie-xform.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
tls-store2.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
tls.ll
…
toc-data-const.ll
Revert "[XCOFF][AIX] Peephole optimization for toc-data."
2023-08-15 10:40:35 -04:00
toc-data.ll
Revert "[XCOFF][AIX] Peephole optimization for toc-data."
2023-08-15 10:40:35 -04:00
toc-float.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
toc-load-sched-bug.ll
[PowerPC] Turn string pooling on by default. (#65628)
2023-09-07 16:49:31 -04:00
tocSaveInPrologue.ll
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
topdepthreduce-postra.mir
…
trampoline.ll
…
trunc-srl-load.ll
…
two-address-crash.mir
…
uint-to-fp-v4i32.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
uint-to-ppcfp128-crash.ll
…
umulfixsat.ll
…
umulo-128-legalisation-lowering.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
unal4-std.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
unal-altivec2.ll
…
unal-altivec-wint.ll
…
unal-altivec.ll
…
unal-vec-ldst.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
unal-vec-negarith.ll
…
unaligned-addressing-mode.ll
…
unaligned-dqform-ld.ll
…
unaligned-floats.ll
…
unaligned.ll
…
unreachable-mbb-jtreference-elimination.ll
[PowerPC]set default min-jump-table-entries to 64 on PPC
2023-08-29 21:42:22 -04:00
unsafe-math.ll
…
unwind-dw2-g.ll
…
unwind-dw2.ll
…
urem-lkk.ll
…
urem-seteq-illegal-types.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
urem-vector-lkk.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
use-cr-result-of-dom-icmp-st.ll
…
uwtables.ll
…
v2i64_scalar_to_vector_shuffle.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
v4i32_scalar_to_vector_shuffle.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
v8i16_scalar_to_vector_shuffle.ll
[PowerPC] Optimize VPERM and fix code order for swapping vector operands on LE
2023-09-13 15:00:49 -05:00
v16i8_scalar_to_vector_shuffle.ll
[PowerPC] Optimize VPERM and fix code order for swapping vector operands on LE
2023-09-13 15:00:49 -05:00
vaddsplat.ll
…
varargs-struct-float.ll
…
varargs.ll
…
variable_elem_vec_extracts.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vavg.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vcmp-fold.ll
…
vec_abs.ll
…
vec_absd.ll
…
vec_add_sub_doubleword.ll
…
vec_add_sub_quadword.ll
…
vec_auto_constant.ll
…
vec_br_cmp.ll
…
vec_buildvector_loadstore.ll
…
vec_call.ll
…
vec_clz.ll
…
vec_cmp.ll
…
vec_cmpd_p7.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vec_cmpd.ll
…
vec_cmpq.ll
…
vec_constants.ll
…
vec_conv_fp32_to_i8_elts.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vec_conv_fp32_to_i16_elts.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vec_conv_fp32_to_i64_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_fp64_to_i8_elts.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vec_conv_fp64_to_i16_elts.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
vec_conv_fp64_to_i32_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_fp_to_i_4byte_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_fp_to_i_8byte_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i8_to_fp32_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i8_to_fp64_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i16_to_fp32_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i16_to_fp64_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i32_to_fp64_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i64_to_fp32_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i_to_fp_4byte_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv_i_to_fp_8byte_elts.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_conv.ll
…
vec_extload.ll
…
vec_extract_p9_2.ll
…
vec_extract_p9.ll
…
vec_fmuladd.ll
…
vec_fneg.ll
…
vec_insert_elt.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_insert.ll
…
vec_int_ext.ll
…
vec_int_to_double_shuffle.ll
…
vec_mergeow.ll
…
vec_minmax.ll
…
vec_misaligned.ll
…
vec_mul_even_odd.ll
…
vec_mul.ll
…
vec_perf_shuffle.ll
…
vec_popcnt.ll
…
vec_revb.ll
…
vec_rotate_shift.ll
…
vec_rounding.ll
…
vec_select.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_shift.ll
…
vec_shuffle_le.ll
…
vec_shuffle_p8vector_le.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec_shuffle_p8vector.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vec_shuffle.ll
…
vec_sldwi.ll
…
vec_splat_constant.ll
…
vec_splat.ll
…
vec_sqrt.ll
…
vec_urem_const.ll
…
vec_veqv_vnand_vorc.ll
…
vec_vrsave.ll
…
vec_xxpermdi.ll
…
vec_zero.ll
…
vec-abi-align.ll
…
vec-asm-disabled.ll
…
vec-bswap.ll
…
vec-extract-itofp.ll
…
vec-icmpeq-v2i64-p7.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vec-itofp.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec-min-max.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vec-promote.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec-select.ll
…
vec-trunc2.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec-trunc.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vec-zext-abdu.ll
[DAG] Fold (abds x, y) -> (abdu x, y) iff both args are known positive
2023-06-20 15:31:22 +01:00
vector-constrained-fp-intrinsics.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vector-copysign.ll
…
vector-extend-sign.ll
[PowerPC] remove XXSWAPD after load from CP which is a splat value
2023-02-16 19:21:35 -05:00
vector-identity-shuffle.ll
…
vector-ldst.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vector-llrint.ll
ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (#66924)
2023-10-19 13:05:04 +01:00
vector-lrint.ll
ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (#66924)
2023-10-19 13:05:04 +01:00
vector-merge-store-fp-constants.ll
…
vector-popcnt-128-ult-ugt.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vector-reduce-add.ll
[PowerPC] Update InputOps of Power10 SchedModel
2023-07-07 22:46:22 +08:00
vector-reduce-and.ll
…
vector-reduce-fadd.ll
…
vector-reduce-fmax.ll
…
vector-reduce-fmin.ll
…
vector-reduce-fmul.ll
…
vector-reduce-mul.ll
…
vector-reduce-or.ll
…
vector-reduce-smax.ll
…
vector-reduce-smin.ll
…
vector-reduce-umax.ll
…
vector-reduce-umin.ll
…
vector-reduce-xor.ll
…
vector-rotates.ll
…
vector-rounding-ops.ll
…
vector-sum-sat-bit-side-effect.ll
[PowerPC] remove side effect for some cases for saturate instructions
2023-03-13 21:37:56 -04:00
vector.ll
…
vmladduhm.ll
…
vperm-instcombine.ll
…
vperm-lowering.ll
…
vperm-swap.ll
[PowerPC] Optimize VPERM and fix code order for swapping vector operands on LE
2023-09-13 15:00:49 -05:00
vrsave-inline-asm.ll
…
vrspill.ll
…
vsel-prom.ll
…
vselect-constants.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vsx_builtins.ll
…
vsx_insert_extract_le.ll
…
vsx_scalar_ld_st.ll
…
vsx_shuffle_le.ll
…
vsx-args.ll
…
VSX-DForm-Scalars.ll
…
vsx-div.ll
…
vsx-elementary-arith.ll
…
vsx-fma-m.ll
…
vsx-fma-mutate-trivial-copy.ll
…
vsx-fma-mutate-undef.ll
…
vsx-fma-sp.ll
…
vsx-infl-copy1.ll
…
vsx-infl-copy2.ll
…
vsx-ldst-builtin-le.ll
…
vsx-ldst.ll
…
vsx-minmax.ll
…
vsx-p8.ll
…
vsx-p9.ll
…
vsx-partword-int-loads-and-stores.ll
Reland "[PowerPC] Simplify fp-to-int store optimization"
2023-06-05 13:53:08 +08:00
vsx-recip-est.ll
…
vsx-self-copy.ll
…
vsx-shuffle-le-load.ll
…
vsx-shuffle-le-multiple-uses.ll
…
vsx-spill-norwstore.ll
…
vsx-spill.ll
…
vsx-vec-spill.ll
…
vsx-word-splats.ll
…
VSX-XForm-Scalars.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
vsx.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
vsxD-Form-spills.ll
…
vtable-reloc.ll
…
wa-asm-fpr.ll
…
weak_def_can_be_hidden.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
wide-scalar-shift-legalization.ll
[PowerPC] Define SchedModel for Power8
2023-09-08 15:43:21 +08:00
widen-vec-correctly-be.ll
[PowerPC] Implement SchedModel for Power7
2023-09-13 14:55:07 +08:00
xray-attribute-instrumentation.ll
[XRay] Make xray_fn_idx entries PC-relative
2023-06-20 22:40:56 -07:00
xray-conditional-return.ll
…
xray-ret-is-terminator.ll
…
xray-tail-call-hidden.ll
[XRay][test] Make tests less sensitive to .Ltmp/Ltmp label changes
2023-06-18 13:32:40 -07:00
xray-tail-call-sled.ll
[XRay][test] Make tests less sensitive to .Ltmp/Ltmp label changes
2023-06-18 13:32:40 -07:00
xvcmpeqdp-v2f64.ll
…
xxeval-and-nand.ll
…
xxeval-eqv-nor-or-xor.ll
…
xxleqv_xxlnand_xxlorc.ll
…
xxperm-swap.ll
[PowerPC] Fix the xxperm swap requirements
2023-04-05 20:13:40 -05:00
xxpermdi_mnemonics.s
…
zero-not-run.ll
…
zext-and-cmp.ll
…
zext-bitperm.ll
…
zext-free.ll
…