98f9389f65
To do this:
1. Add PseudoCALLIndirct to match indirect function call.
2. Add PseudoCALL to support parsing and print pseudo `call` in assembly
3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type
while encoding:
auipc ra, func
jalr ra, ra, 0
If we expand PseudoCALL before emitting assembly, we will see auipc and jalr
pair when compile with -S. It's hard for assembly parser to parsing this
pair and identify it's semantic is function call and then insert R_RISCV_CALL
relocation type. Although we could insert R_RISCV_PCREL_HI20 and
R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL.
Due to RISCV relocation design, auipc and jalr pair only can relax to jal with
R_RISCV_CALL + R_RISCV_RELAX relocation types.
We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before
emitting assembly(RISCVAsmPrinter) because we want to preserve call
pseudoinstruction in assembly code. It's more readable and assembly parser
could identify call assembly and insert R_RISCV_CALL relocation type.
Differential Revision: https://reviews.llvm.org/D45859
llvm-svn: 330826
91 lines
3.0 KiB
C++
91 lines
3.0 KiB
C++
//===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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namespace {
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class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit);
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~RISCVELFObjectWriter() override;
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// Return true if the given relocation must be with a symbol rather than
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// section plus offset.
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bool needsRelocateWithSymbol(const MCSymbol &Sym,
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unsigned Type) const override {
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// TODO: this is very conservative, update once RISC-V psABI requirements
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// are clarified.
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return true;
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}
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protected:
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unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
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const MCFixup &Fixup, bool IsPCRel) const override;
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};
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}
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RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
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: MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV,
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/*HasRelocationAddend*/ true) {}
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RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
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unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
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const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const {
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// Determine the type of the relocation
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switch ((unsigned)Fixup.getKind()) {
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default:
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llvm_unreachable("invalid fixup kind!");
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case FK_Data_4:
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return ELF::R_RISCV_32;
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case FK_Data_8:
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return ELF::R_RISCV_64;
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case RISCV::fixup_riscv_hi20:
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return ELF::R_RISCV_HI20;
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case RISCV::fixup_riscv_lo12_i:
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return ELF::R_RISCV_LO12_I;
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case RISCV::fixup_riscv_lo12_s:
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return ELF::R_RISCV_LO12_S;
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case RISCV::fixup_riscv_pcrel_hi20:
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return ELF::R_RISCV_PCREL_HI20;
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case RISCV::fixup_riscv_pcrel_lo12_i:
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return ELF::R_RISCV_PCREL_LO12_I;
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case RISCV::fixup_riscv_pcrel_lo12_s:
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return ELF::R_RISCV_PCREL_LO12_S;
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case RISCV::fixup_riscv_jal:
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return ELF::R_RISCV_JAL;
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case RISCV::fixup_riscv_branch:
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return ELF::R_RISCV_BRANCH;
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case RISCV::fixup_riscv_rvc_jump:
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return ELF::R_RISCV_RVC_JUMP;
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case RISCV::fixup_riscv_rvc_branch:
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return ELF::R_RISCV_RVC_BRANCH;
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case RISCV::fixup_riscv_call:
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return ELF::R_RISCV_CALL;
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}
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}
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std::unique_ptr<MCObjectWriter>
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llvm::createRISCVELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
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bool Is64Bit) {
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return createELFObjectWriter(
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llvm::make_unique<RISCVELFObjectWriter>(OSABI, Is64Bit), OS,
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/*IsLittleEndian=*/true);
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}
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