c98b26d326
Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and G_SEXTLOAD. That is perform widenScalarDst to size given by the target and avoid additional checks in common code. Targets can reorder or add additional rules in LegalizeRuleSet for the opcode to achieve desired behavior. Select extending load that does not have specified type of extension into zero extending load. Select truncating store that stores number of bytes indicated by size in MachineMemoperand. Differential Revision: https://reviews.llvm.org/D57454 llvm-svn: 353520
359 lines
12 KiB
C++
359 lines
12 KiB
C++
//===- MipsInstructionSelector.cpp ------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// Mips.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "MipsRegisterBankInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#define DEBUG_TYPE "mips-isel"
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using namespace llvm;
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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class MipsInstructionSelector : public InstructionSelector {
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public:
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MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI,
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const MipsRegisterBankInfo &RBI);
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bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
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static const char *getName() { return DEBUG_TYPE; }
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private:
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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const MipsTargetMachine &TM;
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const MipsSubtarget &STI;
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const MipsInstrInfo &TII;
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const MipsRegisterInfo &TRI;
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const MipsRegisterBankInfo &RBI;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // end anonymous namespace
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#define GET_GLOBALISEL_IMPL
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_IMPL
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MipsInstructionSelector::MipsInstructionSelector(
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const MipsTargetMachine &TM, const MipsSubtarget &STI,
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const MipsRegisterBankInfo &RBI)
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: InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
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TRI(*STI.getRegisterInfo()), RBI(RBI),
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#define GET_GLOBALISEL_PREDICATES_INIT
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_INIT
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#define GET_GLOBALISEL_TEMPORARIES_INIT
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_INIT
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{
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}
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static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) {
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unsigned DstReg = I.getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(DstReg))
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return true;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
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<< " operand\n");
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return false;
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}
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return true;
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}
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/// Returning Opc indicates that we failed to select MIPS instruction opcode.
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static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
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if (Opc == TargetOpcode::G_STORE)
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switch (MemSizeInBytes) {
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case 4:
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return Mips::SW;
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case 2:
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return Mips::SH;
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case 1:
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return Mips::SB;
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default:
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return Opc;
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}
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else
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// Unspecified extending load is selected into zeroExtending load.
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switch (MemSizeInBytes) {
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case 4:
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return Mips::LW;
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case 2:
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return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
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case 1:
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return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu;
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default:
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return Opc;
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}
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}
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bool MipsInstructionSelector::select(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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if (!isPreISelGenericOpcode(I.getOpcode())) {
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if (I.isCopy())
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return selectCopy(I, TII, MRI, TRI, RBI);
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return true;
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}
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if (selectImpl(I, CoverageInfo)) {
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return true;
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}
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MachineInstr *MI = nullptr;
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using namespace TargetOpcode;
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switch (I.getOpcode()) {
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case G_GEP: {
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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.add(I.getOperand(2));
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break;
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}
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case G_FRAME_INDEX: {
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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.addImm(0);
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break;
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}
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case G_STORE:
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case G_LOAD:
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case G_ZEXTLOAD:
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case G_SEXTLOAD: {
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const unsigned DestReg = I.getOperand(0).getReg();
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const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
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const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
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const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();
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if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
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return false;
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const unsigned NewOpc =
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selectLoadStoreOpCode(I.getOpcode(), OpMemSizeInBytes);
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if (NewOpc == I.getOpcode())
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return false;
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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.addImm(0)
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.addMemOperand(*I.memoperands_begin());
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break;
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}
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case G_UDIV:
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case G_UREM:
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case G_SDIV:
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case G_SREM: {
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unsigned HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
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bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
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bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV;
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MachineInstr *PseudoDIV, *PseudoMove;
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PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(),
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TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
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.addDef(HILOReg)
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.add(I.getOperand(1))
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.add(I.getOperand(2));
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if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
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return false;
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PseudoMove = BuildMI(MBB, I, I.getDebugLoc(),
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TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
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.addDef(I.getOperand(0).getReg())
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.addUse(HILOReg);
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if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
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return false;
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I.eraseFromParent();
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return true;
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}
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case G_SELECT: {
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// Handle operands with pointer type.
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
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.add(I.getOperand(0))
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.add(I.getOperand(2))
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.add(I.getOperand(1))
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.add(I.getOperand(3));
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break;
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}
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case G_CONSTANT: {
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int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
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unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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MachineInstr *LUi, *ORi;
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LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
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.addDef(LUiReg)
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.addImm(Imm >> 16);
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ORi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ORi))
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.addDef(I.getOperand(0).getReg())
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.addUse(LUiReg)
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.addImm(Imm & 0xFFFF);
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if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
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return false;
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if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
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return false;
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I.eraseFromParent();
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return true;
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}
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case G_GLOBAL_VALUE: {
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if (MF.getTarget().isPositionIndependent())
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return false;
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const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
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unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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MachineInstr *LUi, *ADDiu;
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LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
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.addDef(LUiReg)
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.addGlobalAddress(GVal);
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LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI);
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ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
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.addDef(I.getOperand(0).getReg())
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.addUse(LUiReg)
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.addGlobalAddress(GVal);
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ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
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if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
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return false;
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if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
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return false;
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I.eraseFromParent();
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return true;
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}
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case G_ICMP: {
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struct Instr {
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unsigned Opcode, Def, LHS, RHS;
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Instr(unsigned Opcode, unsigned Def, unsigned LHS, unsigned RHS)
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: Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
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bool hasImm() const {
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if (Opcode == Mips::SLTiu || Opcode == Mips::XORi)
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return true;
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return false;
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}
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};
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SmallVector<struct Instr, 2> Instructions;
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unsigned ICMPReg = I.getOperand(0).getReg();
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unsigned Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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unsigned LHS = I.getOperand(2).getReg();
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unsigned RHS = I.getOperand(3).getReg();
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CmpInst::Predicate Cond =
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static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
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switch (Cond) {
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case CmpInst::ICMP_EQ: // LHS == RHS -> (LHS ^ RHS) < 1
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Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
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Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
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break;
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case CmpInst::ICMP_NE: // LHS != RHS -> 0 < (LHS ^ RHS)
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Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
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Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
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break;
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case CmpInst::ICMP_UGT: // LHS > RHS -> RHS < LHS
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Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
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break;
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case CmpInst::ICMP_UGE: // LHS >= RHS -> !(LHS < RHS)
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Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
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Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
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break;
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case CmpInst::ICMP_ULT: // LHS < RHS -> LHS < RHS
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Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS);
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break;
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case CmpInst::ICMP_ULE: // LHS <= RHS -> !(RHS < LHS)
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Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS);
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Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
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break;
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case CmpInst::ICMP_SGT: // LHS > RHS -> RHS < LHS
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Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS);
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break;
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case CmpInst::ICMP_SGE: // LHS >= RHS -> !(LHS < RHS)
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Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS);
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Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
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break;
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case CmpInst::ICMP_SLT: // LHS < RHS -> LHS < RHS
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Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS);
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break;
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case CmpInst::ICMP_SLE: // LHS <= RHS -> !(RHS < LHS)
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Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS);
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Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
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break;
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default:
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return false;
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}
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MachineIRBuilder B(I);
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for (const struct Instr &Instruction : Instructions) {
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MachineInstrBuilder MIB = B.buildInstr(
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Instruction.Opcode, {Instruction.Def}, {Instruction.LHS});
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if (Instruction.hasImm())
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MIB.addImm(Instruction.RHS);
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else
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MIB.addUse(Instruction.RHS);
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if (!MIB.constrainAllUses(TII, TRI, RBI))
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return false;
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}
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I.eraseFromParent();
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return true;
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}
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default:
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return false;
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}
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I.eraseFromParent();
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return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
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}
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namespace llvm {
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InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
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MipsSubtarget &Subtarget,
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MipsRegisterBankInfo &RBI) {
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return new MipsInstructionSelector(TM, Subtarget, RBI);
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}
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} // end namespace llvm
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