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ca9583a70aebf5ae3ba6fe615e577fc8da9e64a1
clang-p2996/llvm/test/CodeGen/RISCV
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Alex Bradbury 7539fa2c2d [RISCV] Implement RV64D codegen 
This patch:
* Adds necessary RV64D codegen patterns
* Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI)

Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type.

Differential Revision: https://reviews.llvm.org/D53237

llvm-svn: 352833
2019-02-01 03:53:30 +00:00
..
addc-adde-sube-subc.ll
…
align.ll
…
alloca.ll
…
alu8.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
alu16.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
alu32.ll
[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
2019-01-12 07:32:31 +00:00
alu64.ll
[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
2019-01-12 07:32:31 +00:00
analyze-branch.ll
…
arith-with-overflow.ll
[RISCV] Add tests for overflow intrinsics
2018-06-19 06:45:47 +00:00
atomic-cmpxchg.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
atomic-fence.ll
[RISCV][NFC] Add CHECK lines for atomic operations on RV64I
2019-01-11 19:46:48 +00:00
atomic-load-store.ll
[RISCV] Add codegen support for RV64A
2019-01-17 10:04:39 +00:00
atomic-rmw.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
bare-select.ll
…
blockaddress.ll
…
branch-relaxation.ll
…
branch.ll
…
bswap-ctlz-cttz-ctpop.ll
…
byval.ll
…
calling-conv-rv32f-ilp32.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
calling-conv-sext-zext.ll
…
calling-conv.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
calls.ll
…
compress-inline-asm.ll
…
compress.ll
…
disable-tail-calls.ll
…
div.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
double-arith.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-bitmanip-dagcombines.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-br-fcmp.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-calling-conv.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
double-convert.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-fcmp.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-frem.ll
[RISCV] Mark FREM as Expand
2018-11-15 14:46:11 +00:00
double-imm.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-intrinsics.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-mem.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-previous-failure.ll
…
double-select-fcmp.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-stack-spill-restore.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
fixups-diff.ll
[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true
2018-08-16 11:26:37 +00:00
fixups-relax-diff.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
float-arith.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-bitmanip-dagcombines.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-br-fcmp.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-convert.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-fcmp.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-frem.ll
[RISCV] Mark FREM as Expand
2018-11-15 14:46:11 +00:00
float-imm.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-intrinsics.ll
[SelectionDAG] Support promotion of the FPOWI integer operand
2019-02-01 03:46:28 +00:00
float-mem.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-select-fcmp.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
flt-rounds.ll
[SelectionDAG] Support result type promotion for FLT_ROUNDS_
2018-11-30 13:18:33 +00:00
fp128.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
frame.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
frameaddr-returnaddr.ll
[SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands
2018-11-30 10:02:06 +00:00
get-setcc-result-type.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
hoist-global-addr-base.ll
[RISCV] Add machine function pass to merge base + offset
2018-06-27 20:51:42 +00:00
i32-icmp.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
imm-cse.ll
…
imm.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
indirectbr.ll
[RISC-V] Fix a test case to not include label names as those aren't
2018-06-21 05:42:05 +00:00
init-array.ll
…
inline-asm.ll
…
interrupt-attr-args-error.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-invalid.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-nocall.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-ret-error.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
jumptable.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
large-stack.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll
…
mem64.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
mem.ll
…
mul.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
musttail-call.ll
…
option-norelax.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
option-norvc.ll
…
option-relax.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
option-rvc.ll
…
pr40333.ll
[RISCV] Custom-legalise 32-bit variable shifts on RV64
2019-01-25 05:04:00 +00:00
prefetch.ll
[SelectionDAG] Support promotion of PREFETCH operands
2018-11-30 10:06:31 +00:00
rem.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
remat.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
rotl-rotr.ll
…
rv32i-rv64i-float-double.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
rv64d-double-convert.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
rv64f-float-convert.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
rv64i-exhaustive-w-insts.ll
[RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions
2019-01-12 07:32:31 +00:00
rv64i-tricky-shifts.ll
[RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases
2018-12-01 05:00:00 +00:00
rv64m-exhaustive-w-insts.ll
[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
2019-01-25 05:11:34 +00:00
select-cc.ll
…
sext-zext-trunc.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
shift-masked-shamt.ll
[RISCV] Eliminate unnecessary masking of promoted shift amounts
2018-10-12 23:18:52 +00:00
shifts.ll
…
tail-calls.ll
[RISCV] Fixed test case failure due to r338047
2018-07-31 00:36:28 +00:00
umulo-128-legalisation-lowering.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
vararg.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
wide-mem.ll
…
zext-with-load-is-free.ll
…