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cd7eaaa6db0dc9a00a097ba8e6ebad6fb2dec56a
clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel
History
Jay Foad 08da7ac80c [AMDGPU] Fix broken sign-extended subword buffer load combine (#77470)
2024-01-10 10:50:13 +00:00
..
add_shl.ll
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add.v2i16.ll
AMDGPU: Fix packed 16-bit inline constants (#76522)
2024-01-04 00:10:15 +01:00
add.vni16.ll
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addo.ll
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addsubu64.ll
[AMDGPU] CodeGen for GFX12 64-bit scalar add/sub (#75070)
2023-12-12 17:41:40 +00:00
amdgpu-irtranslator.ll
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amdgpu-prelegalizer-combiner-crash.mir
GlobalISel: Guard return in llvm::getIConstantSplatVal (#71989)
2023-11-14 12:23:54 -08:00
andn2.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
artifact-combiner-anyext.mir
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artifact-combiner-asserts.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
artifact-combiner-build-vector.mir
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artifact-combiner-concat-vectors.mir
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artifact-combiner-cse-leaves-dead-cast.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
artifact-combiner-extract.mir
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artifact-combiner-sext.mir
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artifact-combiner-trunc.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
artifact-combiner-unmerge-values.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
artifact-combiner-zext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
ashr.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
assert-align.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
atomic_load_local.ll
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atomic_optimizations_mul_one.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
atomic_store_local.ll
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atomicrmw_udec_wrap.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
atomicrmw_uinc_wrap.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
bool-legalization.ll
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br-constant-invalid-sgpr-copy.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
bswap.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
buffer-atomic-fadd.f32-rtn.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
buffer-atomic-fadd.f64.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-atomic-fadd.v2f16-rtn.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-schedule.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
bug-legalization-artifact-combiner-dead-def.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
bug-legalization-artifact-combiner-dead-def.mir
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call-outgoing-stack-args.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
clamp-fmed3-const-combine.ll
[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)
2023-12-13 13:52:40 +01:00
clamp-minmax-const-combine.ll
[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)
2023-12-13 13:52:40 +01:00
combine-add-nullptr.mir
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combine-add-to-ptradd.mir
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combine-amdgpu-cvt-f32-ubyte.mir
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combine-ashr-narrow.mir
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combine-ext-legalizer.mir
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combine-fabs-fneg.mir
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combine-fcanonicalize.mir
AMDGPU: Fix broken denormal constant folding of canonicalize
2023-07-17 19:54:20 -04:00
combine-fma-add-ext-fma.ll
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combine-fma-add-ext-mul.ll
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combine-fma-add-fma-mul.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-fma-add-mul-post-legalize.mir
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combine-fma-add-mul-pre-legalize.mir
[AMDGPU] Regen combine-fma-add-mul-pre-legalize.mir
2023-09-12 08:50:12 +02:00
combine-fma-add-mul.ll
[GISel] Combine (Scalarize) vector load followed by an element extract.
2023-12-06 11:23:23 +05:30
combine-fma-sub-ext-mul.ll
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combine-fma-sub-ext-neg-mul.ll
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combine-fma-sub-mul.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-fma-sub-neg-mul.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-fma-unmerge-values.mir
AMDGPU: Partially fix not respecting dynamic denormal mode
2023-07-11 15:14:52 -04:00
combine-fold-binop-into-select.mir
[GlobalIsel] Combine selects with constants (#76089)
2024-01-02 17:26:39 +01:00
combine-foldable-fneg.mir
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combine-fsh.mir
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combine-fsub-fneg.mir
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combine-itofp.mir
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combine-lshr-narrow.mir
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combine-or-redundant.mir
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combine-redundant-and.mir
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combine-redundant-neg.mir
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combine-rot.mir
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combine-rsq.ll
AMDGPU: Correctly lower llvm.sqrt.f32
2023-09-12 23:22:54 +03:00
combine-rsq.mir
AMDGPU: Fix more unsafe rsq formation
2023-08-23 19:28:49 -04:00
combine-sext-inreg.mir
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combine-shift-imm-chain-illegal-types.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shift-imm-chain-shlsat.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
combine-shift-imm-chain.ll
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combine-shift-of-shifted-logic-shlsat.mir
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combine-shift-of-shifted-logic.ll
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combine-shl-from-extend-narrow.postlegal.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shl-from-extend-narrow.prelegal.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shl-narrow.mir
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combine-short-clamp.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
combine-trunc-shift.mir
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combine-urem-pow-2.mir
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combine-zext-trunc.mir
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combiner-crash.ll
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compute-num-sign-bits-med3.mir
AMDGPU: Implement known bits functions for min3/max3/med3
2023-06-10 10:58:44 -04:00
constant-bus-restriction.ll
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crash-stack-address-O0.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
cvt_f32_ubyte.ll
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dereferenceable-declaration.ll
[GlobalISel] introduce MIFlag::NoConvergent
2023-08-20 21:14:46 +05:30
divergence-divergent-i1-phis-no-lane-mask-merging.ll
[GlobalIsel] Combine selects with constants (#76089)
2024-01-02 17:26:39 +01:00
divergence-divergent-i1-phis-no-lane-mask-merging.mir
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergence-divergent-i1-used-outside-loop.ll
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergence-divergent-i1-used-outside-loop.mir
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergence-structurizer.ll
[GlobalIsel] Combine selects with constants (#76089)
2024-01-02 17:26:39 +01:00
divergence-structurizer.mir
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergence-temporal-divergent-i1.ll
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergence-temporal-divergent-i1.mir
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergence-temporal-divergent-reg.ll
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergence-temporal-divergent-reg.mir
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
2023-12-13 16:42:56 +01:00
divergent-control-flow.ll
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dropped_debug_info_assert.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
dummy-target.ll
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dynamic-alloca-divergent.ll
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dynamic-alloca-uniform.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
extractelement-stack-lower.ll
[AMDGPU] Remove some unused check prefixes
2024-01-04 13:16:46 +00:00
extractelement.i8.ll
[GISel] Combine (Scalarize) vector load followed by an element extract.
2023-12-06 11:23:23 +05:30
extractelement.i16.ll
[GISel] Combine (Scalarize) vector load followed by an element extract.
2023-12-06 11:23:23 +05:30
extractelement.i128.ll
[GISel] Combine (Scalarize) vector load followed by an element extract.
2023-12-06 11:23:23 +05:30
extractelement.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
fdiv.f16.ll
[GlobalISel] Fold fmul x, 1.0 -> x (#65379)
2023-09-06 03:14:16 +08:00
fdiv.f32.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
fdiv.f64.ll
[GlobalISel] Fold fmul x, 1.0 -> x (#65379)
2023-09-06 03:14:16 +08:00
flat-atomic-fadd.f32.ll
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
flat-atomic-fadd.f64.ll
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flat-atomic-fadd.v2f16.ll
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flat-scratch-init.gfx.ll
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flat-scratch-init.ll
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flat-scratch.ll
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
floor.f64.ll
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fma.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
fmax_legacy.ll
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fmed3-min-max-const-combine.ll
[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)
2023-12-13 13:52:40 +01:00
fmin_legacy.ll
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fmul.v2f16.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
fp64-atomics-gfx90a.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
fp-atomics-gfx940.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
fpow.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
frem.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
fshl.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
fshr.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
function-returns.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
function-returns.v2i65.ll
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global-atomic-fadd.f32-no-rtn.ll
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
global-atomic-fadd.f64.ll
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global-atomic-fadd.v2f16-no-rtn.ll
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global-atomic-fadd.v2f16-rtn.ll
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global-value.illegal.ll
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global-value.ll
[AMDGPU] Tweak handling of GlobalAddress operands in SI_PC_ADD_REL_OFFSET (#70960)
2023-11-01 19:48:30 +00:00
hip.extern.shared.array.ll
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i1-copy.ll
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image-waterfall-loop-O0.ll
[AMDGPU] Try to fix the block prologs broken by RA inserted instructions (#69924)
2023-10-27 19:10:18 +05:30
implicit-kernarg-backend-usage-global-isel.ll
Reland: [AMDGPU] Remove Code Object V3 (#67118)
2023-11-07 12:23:03 +01:00
inline-asm-mismatched-size.ll
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inline-asm.ll
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insertelement-stack-lower.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
insertelement.i8.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
insertelement.i16.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
insertelement.large.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
insertelement.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
inst-select-abs.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-add.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-add.s16.mir
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inst-select-amdgcn.class.mir
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inst-select-amdgcn.class.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.cos.mir
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inst-select-amdgcn.cos.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.cvt.pk.i16.mir
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inst-select-amdgcn.cvt.pk.u16.mir
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inst-select-amdgcn.cvt.pknorm.i16.mir
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inst-select-amdgcn.cvt.pknorm.u16.mir
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inst-select-amdgcn.cvt.pkrtz.mir
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inst-select-amdgcn.ds.swizzle.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.exp.compr.mir
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inst-select-amdgcn.exp.mir
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inst-select-amdgcn.fcmp.constants.w32.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.fcmp.constants.w64.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.fmad.ftz.mir
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inst-select-amdgcn.fmed3.mir
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inst-select-amdgcn.fmed3.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.fract.mir
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inst-select-amdgcn.fract.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.groupstaticsize.mir
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inst-select-amdgcn.mbcnt.lo.mir
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inst-select-amdgcn.mul.u24.mir
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inst-select-amdgcn.mulhi.i24.mir
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inst-select-amdgcn.mulhi.u24.mir
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inst-select-amdgcn.rcp.legacy.mir
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inst-select-amdgcn.rcp.mir
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inst-select-amdgcn.rcp.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.readfirstlane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.reloc.constant.mir
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inst-select-amdgcn.rsq.clamp.mir
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inst-select-amdgcn.rsq.legacy.mir
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inst-select-amdgcn.rsq.mir
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inst-select-amdgcn.rsq.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.s.barrier.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.s.sendmsg.mir
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inst-select-amdgcn.sffbh.mir
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inst-select-amdgcn.sin.mir
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inst-select-amdgcn.sin.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgpu-atomic-cmpxchg-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-amdgpu-ffbh-u32.mir
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inst-select-amdgpu-ffbl-b32.mir
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inst-select-amdgpu-wave-address.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-and.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-anyext.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-ashr.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-ashr.s16.mir
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inst-select-ashr.v2s16.mir
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inst-select-atomic-cmpxchg-local.mir
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inst-select-atomic-cmpxchg-region.mir
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inst-select-atomicrmw-add-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-atomicrmw-add-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-atomicrmw-fadd-local.mir
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inst-select-atomicrmw-fadd-region.mir
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inst-select-atomicrmw-xchg-local.mir
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inst-select-atomicrmw-xchg-region.mir
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inst-select-bitcast.mir
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inst-select-bitreverse.mir
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inst-select-br.mir
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inst-select-brcond.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-bswap.mir
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inst-select-build-vector-trunc.v2s16.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-build-vector.mir
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inst-select-concat-vectors.mir
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inst-select-constant.mir
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
inst-select-copy.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-ctlz-zero-undef.mir
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inst-select-ctpop.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-cttz-zero-undef.mir
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inst-select-extract-vector-elt.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-extract.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-fabs.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-fadd.s16.mir
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inst-select-fadd.s32.mir
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inst-select-fadd.s64.mir
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inst-select-fcanonicalize.mir
[AMDGPU] Switch to using real True16 operands.
2023-09-25 18:21:13 +01:00
inst-select-fceil.mir
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inst-select-fceil.s16.mir
[AMDGPU][True16] Support V_CEIL_F16. (#73108)
2024-01-10 08:46:19 +00:00
inst-select-fcmp.mir
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inst-select-fcmp.s16.mir
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inst-select-fconstant.mir
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
inst-select-fexp2.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
inst-select-ffloor.s16.mir
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inst-select-ffloor.s32.mir
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inst-select-ffloor.s64.mir
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inst-select-fma.s32.mir
…
inst-select-fmad.s32.mir
…
inst-select-fmaxnum-ieee.mir
…
inst-select-fmaxnum-ieee.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fmaxnum-ieee.v2s16.mir
…
inst-select-fmaxnum.mir
…
inst-select-fmaxnum.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fmaxnum.v2s16.mir
…
inst-select-fminnum-ieee.mir
…
inst-select-fminnum-ieee.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fminnum-ieee.v2s16.mir
…
inst-select-fminnum.mir
…
inst-select-fminnum.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fminnum.v2s16.mir
…
inst-select-fmul.mir
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
inst-select-fmul.v2s16.mir
…
inst-select-fneg.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-fptosi.mir
…
inst-select-fptoui.mir
…
inst-select-fract.f64.mir
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
inst-select-frame-index.mir
…
inst-select-freeze.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
inst-select-fshr.mir
…
inst-select-i1-copy.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-icmp.mir
…
inst-select-icmp.s16.mir
…
inst-select-icmp.s64.mir
…
inst-select-implicit-def.mir
…
inst-select-insert-vector-elt.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-insert.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-intrinsic-trunc.mir
…
inst-select-intrinsic-trunc.s16.mir
…
inst-select-inttoptr.mir
…
inst-select-load-atomic-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-atomic-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-atomic-local.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-constant.mir
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
inst-select-load-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-global-saddr.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-global.s96.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-local-128.mir
…
inst-select-load-local.mir
…
inst-select-load-private.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-load-smrd.mir
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
inst-select-lshr.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-lshr.s16.mir
…
inst-select-lshr.v2s16.mir
…
inst-select-mad_64_32.mir
…
inst-select-merge-values.mir
…
inst-select-mul.mir
…
inst-select-or.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-add3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-and-or.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-or3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-smed3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-smed3.s16.mir
…
inst-select-pattern-umed3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-umed3.s16.mir
…
inst-select-pattern-xor3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-phi.mir
…
inst-select-pseudo-scalar-transcendental.mir
[AMDGPU] Add pseudo scalar trans instructions for GFX12 (#75204)
2023-12-15 10:41:05 +01:00
inst-select-ptr-add.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-ptrmask.mir
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
inst-select-ptrtoint.mir
…
inst-select-returnaddress.mir
…
inst-select-sbfx.mir
…
inst-select-scalar-float-sop1.mir
[AMDGPU] Generic lowering for rint and nearbyint (#69596)
2023-11-14 18:49:21 +01:00
inst-select-scalar-float-sop2.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
inst-select-scalar-float-sopc.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
inst-select-scalar-packed.xfail.mir
…
inst-select-select.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-sext-inreg.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-sext.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-sextload-local.mir
…
inst-select-shl.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-shl.s16.mir
…
inst-select-shl.v2s16.mir
…
inst-select-sitofp.mir
…
inst-select-smax.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-smin.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-smulh.mir
…
inst-select-stacksave-stackrestore.invalid.mir
AMDGPU/GlobalISel: Handle stacksave/stackrestore
2023-08-11 10:25:01 -04:00
inst-select-stacksave-stackrestore.mir
AMDGPU/GlobalISel: Handle stacksave/stackrestore
2023-08-11 10:25:01 -04:00
inst-select-store-atomic-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-store-atomic-local.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-store-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-store-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-store-global.s96.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-store-local.mir
…
inst-select-store-private.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
inst-select-sub.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-trunc.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-trunc.v2s16.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-uadde.gfx10.mir
…
inst-select-uadde.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-uaddo.mir
…
inst-select-ubfx.mir
…
inst-select-uitofp.mir
…
inst-select-umax.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-umin.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-umulh.mir
…
inst-select-unmerge-values.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-usube.gfx10.mir
…
inst-select-usube.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-usubo.mir
…
inst-select-xor.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-zext.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-zextload-local.mir
…
irtranslator-amdgcn-cs-chain.ll
[AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (#68186)
2023-11-06 12:30:07 +01:00
irtranslator-amdgcn-sendmsg.ll
…
irtranslator-amdgpu_kernel-system-sgprs.ll
AMDGPU: Don't run AMDGPUAttributor with -O0
2023-06-08 07:52:37 -04:00
irtranslator-amdgpu_kernel.ll
AMDGPU: Don't run AMDGPUAttributor with -O0
2023-06-08 07:52:37 -04:00
irtranslator-amdgpu_ps.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-amdgpu_vs.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-assert-align.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-atomicrmw.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-call-abi-attribute-hints.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-call-implicit-args.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-call-non-fixed.ll
[GlobalISel] introduce MIFlag::NoConvergent
2023-08-20 21:14:46 +05:30
irtranslator-call-return-values.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-call-sret.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-call.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-constant-fold-vector-op.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-constantexpr.ll
[IR] Remove FP cast constant expressions (#71408)
2023-11-07 09:34:16 +01:00
irtranslator-constrained-fp.ll
…
irtranslator-fast-math-flags.ll
…
irtranslator-fence.ll
…
irtranslator-fixed-function-abi-vgpr-args.ll
…
irtranslator-function-args.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-function-args.v2i65.ll
…
irtranslator-getelementptr.ll
…
irtranslator-indirect-call.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-inline-asm.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-invariant.ll
…
irtranslator-memory-intrinsics.ll
…
irtranslator-metadata.ll
…
irtranslator-non-integral-address-spaces-vectors.ll
…
irtranslator-non-integral-address-spaces.ll
…
irtranslator-prefetch.ll
[GlobalISel] Add G_PREFETCH (#74863)
2023-12-11 11:06:50 +00:00
irtranslator-ptrmask.ll
[IR] Require that ptrmask mask matches pointer index size (#69343)
2023-10-24 09:54:29 +02:00
irtranslator-readnone-intrinsic-callsite.ll
…
irtranslator-sat.ll
…
irtranslator-sibling-call.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-struct-return-intrinsics.ll
…
irtranslator-tail-call.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
irtranslator-zext-vec-index.ll
…
lds-global-value.ll
…
lds-misaligned-bug.ll
…
lds-relocs.ll
…
lds-zero-initializer.ll
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
legalize-abs.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-add.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-addrspacecast.mir
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
legalize-amdgcn.if-invalid.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-amdgcn.if.xfail.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
…
legalize-and.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-anyext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ashr.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-atomic-cmpxchg-with-success.mir
…
legalize-atomic-cmpxchg.mir
…
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd-global.mir
…
legalize-atomicrmw-fadd-local.mir
…
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
…
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
…
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-bitreverse.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-block-addr.mir
…
legalize-brcond.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-bswap.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-build-vector-splat.mir
…
legalize-build-vector-trunc.mir
…
legalize-build-vector.mir
…
legalize-build-vector.s16.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
…
legalize-ctlz-zero-undef.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ctlz.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ctpop.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-cttz-zero-undef.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
legalize-cttz.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-extract-vector-elt.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
legalize-extract.mir
…
legalize-extractelement-crash.mir
…
legalize-fabs.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fadd.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fcanonicalize.mir
…
legalize-fceil.mir
…
legalize-fcmp-s32.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
legalize-fcmp.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
legalize-fconstant.mir
…
legalize-fcopysign.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fcos.mir
…
legalize-fdiv.mir
AMDGPU: Always use v_rcp_f16 and v_rsq_f16
2023-07-05 16:53:01 -04:00
legalize-fexp2.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fexp.mir
[AMDGPU] Generic lowering for rint and nearbyint (#69596)
2023-11-14 18:49:21 +01:00
legalize-ffloor.mir
…
legalize-flog2.mir
AMDGPU: Use correct lowering for llvm.log2.f32
2023-06-23 08:37:37 -04:00
legalize-flog10.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-flog.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-fma.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fmad.s16.mir
…
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fminnum.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fmul.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fneg.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fpext.mir
…
legalize-fpow.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fpowi.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fptosi.mir
…
legalize-fptoui.mir
…
legalize-fptrunc.mir
…
legalize-freeze.mir
…
legalize-fshl.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fshr.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fsin.mir
…
legalize-fsqrt.mir
AMDGPU: Correctly lower llvm.sqrt.f32
2023-09-12 23:22:54 +03:00
legalize-fsub.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-icmp.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-implicit-def-s1025.mir
…
legalize-implicit-def.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-insert-vector-elt.mir
…
legalize-insert.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
AMDGPU: Use hex floats instead of ugly bitcasting
2023-07-17 19:54:04 -04:00
legalize-intrinsic-round.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-intrinsic-trunc.mir
…
legalize-inttoptr.mir
…
legalize-jump-table.mir
…
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.dim.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-llvm.amdgcn.image.load.2d.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.load.3d.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.sample.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.sample.d.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.sample.g16.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.sample.g16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.s.buffer.load.mir
[AMDGPU] CodeGen for SMEM instructions (#75579)
2023-12-15 12:10:33 +01:00
legalize-load-constant-32bit.mir
…
legalize-load-constant.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-load-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-load-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-load-local.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-load-memory-metadata.mir
…
legalize-load-private.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-lshr.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-memcpy.mir
…
legalize-memcpyinline.mir
…
legalize-memmove.mir
…
legalize-memset.mir
…
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-mul.mir
[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825)
2024-01-08 19:13:38 +00:00
legalize-or.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-phi.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ptr-add.mir
…
legalize-ptrmask.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ptrtoint.mir
…
legalize-rotl-rotr.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sadde.mir
…
legalize-saddo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-saddsat.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sbfx.mir
…
legalize-sdiv.mir
…
legalize-select.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sext-inreg.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sextload-constant-32bit.mir
…
legalize-sextload-flat.mir
…
legalize-sextload-global.mir
…
legalize-sextload-local.mir
…
legalize-sextload-private.mir
…
legalize-shl.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-shuffle-vector.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-shuffle-vector.s16.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sitofp.mir
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
legalize-smax.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-smin.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-smulh.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-smulo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-srem.mir
…
legalize-sshlsat.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ssube.mir
…
legalize-ssubo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ssubsat.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-store-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-store.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-strict_fsub.mir
…
legalize-sub.mir
…
legalize-trap.mir
AMDGPU: Avoid endpgm in middle of block for fallback trap lowering.
2023-06-09 21:04:38 -04:00
legalize-trunc.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-uadde.mir
…
legalize-uaddo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-uaddsat.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ubfx.mir
…
legalize-udiv.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-uitofp.mir
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
legalize-umax.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-umin.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-umulh.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-umulo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-unmerge-values.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-urem.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ushlsat.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-usube.mir
…
legalize-usubo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-usubsat.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-vector-args-gfx7.mir
…
legalize-vector-args-gfx8-plus.mir
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-xor.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-zext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-zextload-constant-32bit.mir
…
legalize-zextload-flat.mir
…
legalize-zextload-global.mir
…
legalize-zextload-local.mir
…
legalize-zextload-private.mir
…
llvm.abs.ll
[AMDGPU][GlobalISel] Update applyMappingImpl for G_ABS and type v2s16
2023-08-02 12:27:06 +02:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Move ballot64 wave32 mode tests to the appropriate place. NFC. (#72959)
2023-11-21 08:29:15 +01:00
llvm.amdgcn.ballot.i64.ll
Improve selection of conditional branch on amdgcn.ballot!=0 condition in SelectionDAG. (#68714)
2023-11-06 15:16:49 +01:00
llvm.amdgcn.dispatch.id.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.div.fmas.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
llvm.amdgcn.ds.fadd.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.ds.fmax.ll
…
llvm.amdgcn.ds.fmin.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.end.cf.i32.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.end.cf.i64.ll
…
llvm.amdgcn.fdot2.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.fmul.legacy.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
llvm.amdgcn.global.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.global.atomic.fadd.ll
…
llvm.amdgcn.if.break.i32.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.if.break.i64.ll
…
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.atomic.dim.mir
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.gather4.o.dim.ll
…
llvm.amdgcn.image.getresinfo.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.getresinfo.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.load.1d.d16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.load.1d.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.load.2d.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.load.3d.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.load.3d.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.sample.cd.g16.ll
…
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.store.2d.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.implicit.ptr.buffer.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
llvm.amdgcn.interp.inreg.ll
[AMDGPU] NFC. Run auto-update on a few tests
2023-11-21 13:52:02 -05:00
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
llvm.amdgcn.is.private.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
llvm.amdgcn.is.shared.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
llvm.amdgcn.kernarg.segment.ptr.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.make.buffer.rsrc.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.mfma.gfx90a.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.queue.ptr.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.raw.buffer.atomic.add.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] CodeGen for 64-bit buffer atomic cmpswap intrinsics (#70475)
2023-10-30 16:44:22 +00:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.rsq.clamp.ll
[AMDGPU] Add pseudo scalar trans instructions for GFX12 (#75204)
2023-12-15 10:41:05 +01:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sdot2.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.sdot4.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
llvm.amdgcn.sdot8.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.set.inactive.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.struct.buffer.atomic.add.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Fix broken sign-extended subword buffer load combine (#77470)
2024-01-10 10:50:13 +00:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] CodeGen for 64-bit buffer atomic cmpswap intrinsics (#70475)
2023-10-30 16:44:22 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.sudot4.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.sudot8.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.trig.preop.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.ubfe.ll
…
llvm.amdgcn.udot2.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.udot4.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
llvm.amdgcn.udot8.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.update.dpp.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.wmma_32.ll
[AMDGPU][wmma] - Add tied wmma intrinsic (#69903)
2023-10-30 16:23:49 +01:00
llvm.amdgcn.wmma_64.ll
[AMDGPU][wmma] - Add tied wmma intrinsic (#69903)
2023-10-30 16:23:49 +01:00
llvm.amdgcn.workgroup.id.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.workitem.id.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.wqm.demote.ll
…
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
…
llvm.memcpy.inline.ll
CodeGen: Expand memory intrinsics in PreISelIntrinsicLowering
2023-06-09 21:04:37 -04:00
llvm.memcpy.ll
CodeGen: Expand memory intrinsics in PreISelIntrinsicLowering
2023-06-09 21:04:37 -04:00
llvm.memmove.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
llvm.memset.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
llvm.powi.ll
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
load-constant32bit.ll
…
load-constant.96.ll
[AMDGPU] CodeGen for SMEM instructions (#75579)
2023-12-15 12:10:33 +01:00
load-local.96.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
load-local.128.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
load-unaligned.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
localizer-wrong-insert-point.mir
…
localizer.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
lshr.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
memory-legalizer-atomic-fence.ll
[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)
2023-12-15 12:33:32 +01:00
merge-buffer-stores.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
minmaxabs.ll
…
mubuf-global.ll
[AMDGPU] Add new cache flushing instructions for GFX12 (#76944)
2024-01-08 14:06:58 +00:00
mul-known-bits.i64.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
mul-known-bits.i64.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
mul.ll
[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825)
2024-01-08 19:13:38 +00:00
mul.v2i16.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
no-cse-nonlocal-convergent-instrs.mir
…
no-legalize-atomic.mir
…
non-entry-alloca.ll
[AMDGPU][GlobalISel] Update tests to check for COV5 (#76257)
2024-01-03 17:53:47 +05:30
orn2.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
postlegalizer-combiner-buildvector-identities.mir
…
postlegalizer-combiner-divrem.mir
…
postlegalizer-combiner-fcanonicalize.mir
…
postlegalizer-combiner-freeze.mir
…
postlegalizer-combiner-reassoc.mir
[GlobalISel] Fix infinite loop in reassociation combine
2023-07-16 14:15:24 +01:00
postlegalizer-combiner-sextload-from-sextinreg.mir
…
postlegalizer-combiner-trunc-bitcast-buildvector.mir
…
postlegalizer-combiner-unmerge-undef.mir
…
postlegalizer-combiner-zextload-from-and.mir
…
postlegalizercombiner-and.mir
…
postlegalizercombiner-ashr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-load-and-mask.mir
…
postlegalizercombiner-lshr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-mul.mir
[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825)
2024-01-08 19:13:38 +00:00
postlegalizercombiner-sbfx.mir
…
postlegalizercombiner-select.mir
…
postlegalizercombiner-shl.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-ubfx.mir
…
prelegalizer-combiner-divrem.mir
…
prelegalizer-combiner-fptrunc_fpext.mir
…
prelegalizer-combiner-redundant-bitcast.mir
…
prelegalizer-combiner-sext_inreg-to-and.mir
…
regbankcombiner-clamp-fmed3-const.mir
[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)
2023-12-13 13:52:40 +01:00
regbankcombiner-clamp-minmax-const.mir
…
regbankcombiner-fmed3-minmax-const.mir
…
regbankcombiner-smed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankcombiner-umed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-abs.mir
[AMDGPU][GlobalISel] Update applyMappingImpl for G_ABS and type v2s16
2023-08-02 12:27:06 +02:00
regbankselect-add.s16.mir
…
regbankselect-add.s32.mir
…
regbankselect-add.v2s16.mir
…
regbankselect-amdgcn-exp-compr.mir
…
regbankselect-amdgcn-exp.mir
…
regbankselect-amdgcn-s-buffer-load.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ballot.i64.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.class.mir
…
regbankselect-amdgcn.cvt.pkrtz.mir
…
regbankselect-amdgcn.div.fmas.mir
…
regbankselect-amdgcn.div.scale.mir
…
regbankselect-amdgcn.ds.append.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.bpermute.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.consume.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.gws.init.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.gws.sema.v.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.ordered.add.mir
…
regbankselect-amdgcn.ds.ordered.swap.mir
…
regbankselect-amdgcn.ds.permute.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.swizzle.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.else.32.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.else.64.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.fcmp.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.fmul.legacy.mir
…
regbankselect-amdgcn.groupstaticsize.mir
…
regbankselect-amdgcn.icmp.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.image.load.1d.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.image.sample.1d.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.interp.mov.mir
…
regbankselect-amdgcn.interp.p1.f16.mir
…
regbankselect-amdgcn.interp.p1.mir
…
regbankselect-amdgcn.interp.p2.f16.mir
…
regbankselect-amdgcn.interp.p2.mir
…
regbankselect-amdgcn.kernarg.segment.ptr.mir
…
regbankselect-amdgcn.kill.mir
…
regbankselect-amdgcn.lds.direct.load.mir
…
regbankselect-amdgcn.lds.param.load.mir
…
regbankselect-amdgcn.live.mask.mir
…
regbankselect-amdgcn.mfma.gfx90a.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.mfma.gfx940.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.mfma.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ps.live.mir
…
regbankselect-amdgcn.raw.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.raw.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.readfirstlane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.readlane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.s.buffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
regbankselect-amdgcn.s.buffer.load.mir
…
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
…
regbankselect-amdgcn.s.getpc.mir
…
regbankselect-amdgcn.s.getreg.mir
…
regbankselect-amdgcn.s.memrealtime.mir
…
regbankselect-amdgcn.s.memtime.mir
…
regbankselect-amdgcn.s.sendmsg.mir
…
regbankselect-amdgcn.s.sendmsghalt.mir
…
regbankselect-amdgcn.struct.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.buffer.store.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.update.dpp.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.wqm.demote.mir
…
regbankselect-amdgcn.wqm.mir
…
regbankselect-amdgcn.wqm.vote.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.writelane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.wwm.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgpu-ffbh-u32.mir
…
regbankselect-amdgpu-ffbl-b32.mir
…
regbankselect-amdgpu-wave-address.mir
AMDGPU/GlobalISel: Use SGPR results for G_AMDGPU_WAVE_ADDRESS
2023-07-31 19:16:11 -04:00
regbankselect-and-s1.mir
…
regbankselect-and.mir
…
regbankselect-anyext.mir
…
regbankselect-ashr.mir
…
regbankselect-assert-align.mir
…
regbankselect-assert-zext.mir
…
regbankselect-atomic-cmpxchg.mir
…
regbankselect-atomicrmw-add.mir
…
regbankselect-atomicrmw-and.mir
…
regbankselect-atomicrmw-fadd.mir
…
regbankselect-atomicrmw-max.mir
…
regbankselect-atomicrmw-min.mir
…
regbankselect-atomicrmw-or.mir
…
regbankselect-atomicrmw-sub.mir
…
regbankselect-atomicrmw-umax.mir
…
regbankselect-atomicrmw-umin.mir
…
regbankselect-atomicrmw-xchg.mir
…
regbankselect-atomicrmw-xor.mir
…
regbankselect-bitcast.mir
…
regbankselect-bitreverse.mir
…
regbankselect-block-addr.mir
…
regbankselect-brcond.mir
…
regbankselect-bswap.mir
…
regbankselect-build-vector.mir
…
regbankselect-concat-vector.mir
…
regbankselect-constant.mir
…
regbankselect-copy.mir
…
regbankselect-ctlz-zero-undef.mir
…
regbankselect-ctpop.mir
…
regbankselect-cttz-zero-undef.mir
…
regbankselect-default.mir
…
regbankselect-dyn-stackalloc.mir
…
regbankselect-extract-vector-elt.mir
…
regbankselect-extract.mir
…
regbankselect-fabs.mir
…
regbankselect-fadd.mir
…
regbankselect-fcanonicalize.mir
…
regbankselect-fceil.mir
…
regbankselect-fcmp.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
regbankselect-fexp2.mir
…
regbankselect-flog2.mir
…
regbankselect-fma.mir
…
regbankselect-fmul.mir
…
regbankselect-fneg.mir
…
regbankselect-fpext.mir
…
regbankselect-fptosi.mir
…
regbankselect-fptoui.mir
…
regbankselect-fptrunc.mir
…
regbankselect-frame-index.mir
…
regbankselect-freeze.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
regbankselect-fshr.mir
…
regbankselect-fsqrt.mir
…
regbankselect-fsub.mir
…
regbankselect-icmp.mir
…
regbankselect-icmp.s16.mir
…
regbankselect-illegal-copy.mir
…
regbankselect-implicit-def.mir
…
regbankselect-insert-vector-elt.mir
…
regbankselect-insert.mir
…
regbankselect-intrinsic-trunc.mir
…
regbankselect-inttoptr.mir
…
regbankselect-load.mir
[AMDGPU] CodeGen for SMEM instructions (#75579)
2023-12-15 12:10:33 +01:00
regbankselect-lshr.mir
…
regbankselect-mad_64_32.mir
…
regbankselect-merge-values.mir
…
regbankselect-mul.mir
[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825)
2024-01-08 19:13:38 +00:00
regbankselect-or.mir
…
regbankselect-phi-s1.mir
…
regbankselect-phi.mir
…
regbankselect-pseudo-scalar-transcendental.mir
[AMDGPU] Add pseudo scalar trans instructions for GFX12 (#75204)
2023-12-15 10:41:05 +01:00
regbankselect-ptr-add.mir
…
regbankselect-ptrmask.mir
…
regbankselect-ptrtoint.mir
…
regbankselect-reg-sequence.mir
…
regbankselect-sadde.mir
…
regbankselect-salu-float.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
regbankselect-sbfx.mir
…
regbankselect-select.mir
…
regbankselect-sext-inreg.mir
…
regbankselect-sext.mir
…
regbankselect-sextload.mir
…
regbankselect-shl.mir
…
regbankselect-sitofp.mir
…
regbankselect-smax.mir
…
regbankselect-smin.mir
…
regbankselect-smulh.mir
…
regbankselect-split-scalar-load-metadata.mir
[AMDGPU] CodeGen for SMEM instructions (#75579)
2023-12-15 12:10:33 +01:00
regbankselect-ssube.mir
…
regbankselect-sub.mir
…
regbankselect-trunc.mir
…
regbankselect-uadde.mir
…
regbankselect-uaddo.mir
…
regbankselect-ubfx.mir
…
regbankselect-uitofp.mir
…
regbankselect-umax.mir
…
regbankselect-umin.mir
…
regbankselect-umulh.mir
…
regbankselect-uniform-load-noclobber.mir
…
regbankselect-unmerge-values.mir
…
regbankselect-usube.mir
…
regbankselect-usubo.mir
…
regbankselect-waterfall-agpr.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-widen-scalar-loads.mir
…
regbankselect-xor.mir
…
regbankselect-zext.mir
…
regbankselect-zextload.mir
…
regbankselect.mir
…
saddsat.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
sbfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
sdiv.i32.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
sdiv.i64.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
sdivrem.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
select-to-fmin-fmax.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
sext_inreg.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
shader-epilogs.ll
…
shl-ext-reduce.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
shl.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
shlN_add.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
smed3.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
smrd.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
srem.i32.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
srem.i64.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
ssubsat.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
store-local.96.ll
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
store-local.128.ll
…
strict_fma.f16.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f32.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f64.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
sub.v2i16.ll
AMDGPU: Fix packed 16-bit inline constants (#76522)
2024-01-04 00:10:15 +01:00
subo.ll
…
trunc.ll
…
uaddsat.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
ubfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
udiv.i32.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
udiv.i64.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
udivrem.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
umed3.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
unsupported-load.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
unsupported-ptr-add.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
urem.i32.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
urem.i64.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
usubsat.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
v_bfe_i32.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
widen-i8-i16-scalar-loads.ll
…
xnor.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
zextload.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00