26dc284498
Lower formal arguments and returns for functions with the `amdgpu_cs_chain` and `amdgpu_cs_chain_preserve` calling conventions: * Put `inreg` arguments into SGPRs, starting at s0, and other arguments into VGPRs, starting at v8. No arguments should end up on the stack, if we don't have enough registers we should error out. * Lower the return (which is always void) as an S_ENDPGM. * Set the ScratchRSrc register to s48:51, as described in the docs. * Set the SP to s32, matching amdgpu_gfx. This might be revisited in a future patch. Differential Revision: https://reviews.llvm.org/D153517
246 lines
10 KiB
TableGen
246 lines
10 KiB
TableGen
//===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the AMD Radeon GPUs.
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//
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//===----------------------------------------------------------------------===//
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// Inversion of CCIfInReg
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class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
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class CCIfExtend<CCAction A>
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: CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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// Calling convention for SI
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def CC_SI_Gfx : CallingConv<[
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// 0-3 are reserved for the stack buffer descriptor
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// 30-31 are reserved for the return address
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// 32 is reserved for the stack pointer
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// 33 is reserved for the frame pointer
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// 34 is reserved for the base pointer
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CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
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SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
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SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
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SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29
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]>>>,
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
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]>>>,
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CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
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]>;
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def RetCC_SI_Gfx : CallingConv<[
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CCIfType<[i1], CCPromoteToType<i32>>,
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CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
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VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
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VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
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VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
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VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
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VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
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VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
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VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
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VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
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VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
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VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
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VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
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VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
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VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
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]>>>,
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]>;
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def CC_SI_SHADER : CallingConv<[
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CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
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SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
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SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
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SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
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SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
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SGPR40, SGPR41, SGPR42, SGPR43
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]>>>,
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// 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
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VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
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VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
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VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
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VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
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VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
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VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
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VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
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VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
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VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
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VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
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VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
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VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
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VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
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]>>>
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]>;
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def RetCC_SI_Shader : CallingConv<[
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CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfType<[i32, i16, v2i16] , CCAssignToReg<[
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SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
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SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
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SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
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SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
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SGPR40, SGPR41, SGPR42, SGPR43
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]>>,
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// 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
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CCIfType<[f32, f16, v2f16] , CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
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VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
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VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
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VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
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VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
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VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
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VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
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VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
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VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
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VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
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VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
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VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
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VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
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VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
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]>>
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]>;
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def CSR_AMDGPU_VGPRs : CalleeSavedRegs<
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// The CSRs & scratch-registers are interleaved at a split boundary of 8.
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(add (sequence "VGPR%u", 40, 47),
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(sequence "VGPR%u", 56, 63),
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(sequence "VGPR%u", 72, 79),
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(sequence "VGPR%u", 88, 95),
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(sequence "VGPR%u", 104, 111),
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(sequence "VGPR%u", 120, 127),
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(sequence "VGPR%u", 136, 143),
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(sequence "VGPR%u", 152, 159),
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(sequence "VGPR%u", 168, 175),
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(sequence "VGPR%u", 184, 191),
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(sequence "VGPR%u", 200, 207),
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(sequence "VGPR%u", 216, 223),
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(sequence "VGPR%u", 232, 239),
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(sequence "VGPR%u", 248, 255))
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>;
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def CSR_AMDGPU_AGPRs : CalleeSavedRegs<
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(sequence "AGPR%u", 32, 255)
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>;
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def CSR_AMDGPU_SGPRs : CalleeSavedRegs<
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(sequence "SGPR%u", 30, 105)
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>;
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def CSR_AMDGPU_SI_Gfx_SGPRs : CalleeSavedRegs<
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(add (sequence "SGPR%u", 4, 31), (sequence "SGPR%u", 64, 105))
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>;
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def CSR_AMDGPU : CalleeSavedRegs<
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(add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs)
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>;
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def CSR_AMDGPU_GFX90AInsts : CalleeSavedRegs<
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(add CSR_AMDGPU, CSR_AMDGPU_AGPRs)
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>;
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def CSR_AMDGPU_SI_Gfx : CalleeSavedRegs<
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(add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SI_Gfx_SGPRs)
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>;
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def CSR_AMDGPU_SI_Gfx_GFX90AInsts : CalleeSavedRegs<
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(add CSR_AMDGPU_SI_Gfx, CSR_AMDGPU_AGPRs)
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>;
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def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
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// Calling convention for leaf functions
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def CC_AMDGPU_Func : CallingConv<[
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CCIfByVal<CCPassByVal<4, 4>>,
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CCIfType<[i1], CCPromoteToType<i32>>,
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CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
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CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
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]>;
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// Calling convention for leaf functions
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def RetCC_AMDGPU_Func : CallingConv<[
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CCIfType<[i1], CCPromoteToType<i32>>,
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CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[
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VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
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VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
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VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
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VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
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]>;
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def CC_AMDGPU : CallingConv<[
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CCIf<"static_cast<const GCNSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() >= "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS",
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CCDelegateTo<CC_SI_SHADER>>,
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CCIf<"static_cast<const GCNSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).getGeneration() >= "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C",
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CCDelegateTo<CC_AMDGPU_Func>>
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]>;
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def CC_AMDGPU_CS_CHAIN : CallingConv<[
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CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<
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!foreach(i, !range(105), !cast<Register>("SGPR"#i))
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>>>,
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<
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!foreach(i, !range(8, 255), !cast<Register>("VGPR"#i))
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>>>
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]>;
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// Trivial class to denote when a def is used only to get a RegMask, i.e.
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// SaveList is ignored and the def is not used as part of any calling
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// convention.
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class RegMask<dag mask> : CalleeSavedRegs<mask>;
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def AMDGPU_AllVGPRs : RegMask<
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(sequence "VGPR%u", 0, 255)
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>;
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def AMDGPU_AllAGPRs : RegMask<
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(sequence "AGPR%u", 0, 255)
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>;
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def AMDGPU_AllVectorRegs : RegMask<
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(add AMDGPU_AllVGPRs, AMDGPU_AllAGPRs)
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>;
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def AMDGPU_AllAllocatableSRegs : RegMask<
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(add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
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>;
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