b78b36e1a2
To reduce the register pressure during allocation, when the allocator spills a virtual register that corresponds to a whole wave mode operation, the spill loads and restores should be activated for all lanes by temporarily flipping all bits in exec register to one just before the spills. It is not implemented in the compiler as of today and this patch enables the necessary support. This is a pre-patch before the SGPR spill to virtual VGPR lanes that would eventually causes the whole wave register spills during allocation. Reviewed By: arsenm, cdevadas Differential Revision: https://reviews.llvm.org/D143759
152 lines
5.3 KiB
C++
152 lines
5.3 KiB
C++
//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// The AMDGPU TargetMachine interface definition for hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
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#include "GCNSubtarget.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Target/TargetMachine.h"
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#include <optional>
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#include <utility>
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namespace llvm {
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//===----------------------------------------------------------------------===//
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// AMDGPU Target Machine (R600+)
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//===----------------------------------------------------------------------===//
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class AMDGPUTargetMachine : public LLVMTargetMachine {
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protected:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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StringRef getGPUName(const Function &F) const;
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StringRef getFeatureString(const Function &F) const;
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public:
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static bool EnableLateStructurizeCFG;
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static bool EnableFunctionCalls;
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static bool EnableLowerModuleLDS;
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AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, TargetOptions Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL);
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~AMDGPUTargetMachine() override;
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const TargetSubtargetInfo *getSubtargetImpl() const;
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const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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void registerPassBuilderCallbacks(PassBuilder &PB) override;
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void registerDefaultAliasAnalyses(AAManager &) override;
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/// Get the integer value of a null pointer in the given address space.
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static int64_t getNullPointerValue(unsigned AddrSpace);
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
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unsigned getAssumedAddrSpace(const Value *V) const override;
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std::pair<const Value *, unsigned>
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getPredicatedAddrSpace(const Value *V) const override;
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unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override;
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};
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//===----------------------------------------------------------------------===//
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// GCN Target Machine (SI+)
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//===----------------------------------------------------------------------===//
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class GCNTargetMachine final : public AMDGPUTargetMachine {
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private:
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mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
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public:
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GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, TargetOptions Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
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bool useIPRA() const override {
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return true;
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}
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void registerMachineRegisterInfoCallback(MachineFunction &MF) const override;
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
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yaml::MachineFunctionInfo *
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convertFuncInfoToYAML(const MachineFunction &MF) const override;
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bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
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PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error,
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SMRange &SourceRange) const override;
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};
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//===----------------------------------------------------------------------===//
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// AMDGPU Pass Setup
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//===----------------------------------------------------------------------===//
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class AMDGPUPassConfig : public TargetPassConfig {
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public:
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AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM);
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AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
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return getTM<AMDGPUTargetMachine>();
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}
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override;
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void addEarlyCSEOrGVNPass();
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void addStraightLineScalarOptimizationPasses();
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void addIRPasses() override;
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void addCodeGenPrepare() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addGCPasses() override;
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std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
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/// Check if a pass is enabled given \p Opt option. The option always
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/// overrides defaults if explicitly used. Otherwise its default will
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/// be used given that a pass shall work at an optimization \p Level
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/// minimum.
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bool isPassEnabled(const cl::opt<bool> &Opt,
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CodeGenOpt::Level Level = CodeGenOpt::Default) const {
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if (Opt.getNumOccurrences())
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return Opt;
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if (TM->getOptLevel() < Level)
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return false;
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return Opt;
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
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