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clang-p2996/llvm/lib/Target/RISCV
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Kito Cheng af9b25f9db [RISCV] Optimize floating point scalar move and splat 
In D158086, we limit all floating point scalar move and splat can't fuse
vsetvli with different SEW, and this patch try to relax the constraint
as possible by introducing new SEW demand type:
SEWGreaterThanOrEqualAndLessThan64, that allow SEW fused with larger
SEW, but constraint it can't fused with SEW=64.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D158177
2023-09-06 16:39:30 +08:00
..
AsmParser
[MC] Change tryParseRegister to return ParseStatus (NFC)
2023-09-06 10:28:12 +03:00
Disassembler
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
GISel
Revert "[RISCV][GlobalISel] Select ALU GPR instructions"
2023-08-28 10:14:26 -07:00
MCA
[RISCV][llvm-mca] Fix Fix getLMUL values
2023-09-05 09:34:47 -07:00
MCTargetDesc
[MC,AArch64] Suppress local symbol to STT_SECTION conversion for GOT relocations
2023-08-29 11:07:12 -07:00
TargetInfo
…
CMakeLists.txt
Revert "[RISCV][GlobalISel] Select ALU GPR instructions"
2023-08-28 10:14:26 -07:00
RISCV.h
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCV.td
…
RISCVAsmPrinter.cpp
Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm"
2023-08-31 14:02:53 -07:00
RISCVCallingConv.td
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
RISCVCodeGenPrepare.cpp
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV][NFC] Add RISCVSubtarget field to RISCVExpandPseudo and RISCVPreRAExpandPseudo
2023-07-21 16:50:11 +01:00
RISCVFeatures.td
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
RISCVFrameLowering.cpp
[RISCV] Adjust first sp size to use c.addi16sp.
2023-09-06 14:26:52 +08:00
RISCVFrameLowering.h
[llvm] Fix duplicate word typos. NFC
2023-09-01 18:25:16 -07:00
RISCVGatherScatterLowering.cpp
[RISCVGatherScatterLowering] Support broadcast base pointer
2023-08-07 07:42:04 -07:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Separate hasRoundModeOpNum into separate VXRM and FRM functions.
2023-08-21 10:00:23 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Optimize floating point scalar move and splat
2023-09-06 16:39:30 +08:00
RISCVInstrFormats.td
[RISCV] Add a common base class for RVInstR variations. NFC
2023-07-31 13:06:23 -07:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrInfo.cpp
[RISCV][GISel] Legalize G_PHI and G_BRCOND.
2023-08-14 10:21:58 -07:00
RISCVInstrInfo.h
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVInstrInfo.td
[RISCV] Remove trailing whitespace. NFC.
2023-08-21 10:01:13 +08:00
RISCVInstrInfoA.td
[RISCV] Remove AtomicStPat now that atomic_store has the same operand order as store. NFC
2023-08-31 19:32:21 -07:00
RISCVInstrInfoC.td
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
RISCVInstrInfoD.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoF.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoM.td
[NFC][RISCV] Rewrite TableGen files using named arguments
2023-07-20 17:17:49 +08:00
RISCVInstrInfoV.td
[RISCV] Add SchedRead for merge operand
2023-08-13 12:25:22 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Split VFWREDUSUM and VFWREDOSUM SchedWrite (#65386)
2023-09-05 13:39:44 -04:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Rename CVROR, NFC
2023-08-20 16:36:03 +10:00
RISCVInstrInfoXSf.td
[RISCV] Simplify some XSfvcp tablegen. NFC
2023-08-11 12:01:57 -07:00
RISCVInstrInfoXTHead.td
[RISCV][NFC] Use named arguments in newly added changes
2023-08-10 17:14:13 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
RISCVInstrInfoZb.td
[RISCV] Use add.uw for (or (and X, 0xFFFFFFFF), Y) if Y has zeroes in the lower 32 bits. (#65402)
2023-09-05 21:05:53 -07:00
RISCVInstrInfoZc.td
[RISCV] Fix rlist grammar for cm.push, cm.popret, cm.popretz and cm.pop in RISCV zcmp Extension
2023-08-15 01:06:41 +08:00
RISCVInstrInfoZfa.td
[RISCV] Simplify tablegen class for Zfa FLI instructions. NFC
2023-07-25 09:33:54 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Remove trailing whitespace from some .td files.
2023-08-11 12:29:20 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Add support for llvm.prefetch to use Zicbop instructions.
2023-06-13 09:51:30 -07:00
RISCVInstrInfoZicond.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZk.td
[RISCV] Add a common base class for RVInstI variations. NFC
2023-07-31 13:03:35 -07:00
RISCVInstrInfoZvfbf.td
[RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.
2023-08-04 09:08:16 -07:00
RISCVInstrInfoZvk.td
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.
2023-08-31 20:24:34 -07:00
RISCVISelDAGToDAG.h
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
RISCVISelLowering.cpp
[RISCV] Cap build vector cost to avoid quadratic cost at high LMULs
2023-09-05 09:03:26 -07:00
RISCVISelLowering.h
[RISCV] Lower vro{l,r} for fixed vectors
2023-08-08 09:47:00 +01:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] Fix incorrect return type of isPushable() to bool. NFC.
2023-07-26 17:04:47 +08:00
RISCVMacroFusion.cpp
…
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
2023-05-16 09:10:49 +01:00
RISCVMergeBaseOffset.cpp
Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm"
2023-08-31 14:02:53 -07:00
RISCVMoveMerger.cpp
[RISCV][NFC] Adjust RISCVMoveMerge.cpp header to match standard style
2023-06-27 13:35:41 +01:00
RISCVOptWInstrs.cpp
[RISCV] Add Zicond instructions to RISCVOptWInstrs like XVentanaCondOps.
2023-08-23 16:57:16 -07:00
RISCVProcessors.td
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
RISCVPushPopOptimizer.cpp
[RISCV] Add bounds check before use on returned iterator.
2023-08-14 16:06:09 -07:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[llvm] Remove SmallSet from MachineInstr.h
2023-08-12 18:15:27 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Remove trailing whitespace. NFC.
2023-08-21 10:01:13 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
RISCVSchedRocket.td
[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
2023-08-24 19:21:36 -07:00
RISCVSchedSiFive7.td
[RISCV] Fix SiFive7 formula for Reductions and ordered Reductions (#65385)
2023-09-05 23:04:21 -04:00
RISCVSchedSyntacoreSCR1.td
[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
2023-08-24 19:21:36 -07:00
RISCVSchedule.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVScheduleV.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[RISCV] Remove XLen field from RISCVSubtarget [nfc]
2023-09-01 07:42:03 -07:00
RISCVSubtarget.h
[RISCV] Remove XLen field from RISCVSubtarget [nfc]
2023-09-01 07:42:03 -07:00
RISCVSystemOperands.td
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
RISCVTargetMachine.cpp
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Rename getELEN to getELen [nfc]
2023-08-31 11:27:00 -07:00
RISCVTargetTransformInfo.h
[RISCV][TTI] Factor out getVSlideCost helper [nfc]
2023-08-22 14:16:51 -07:00