a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
315 lines
10 KiB
LLVM
315 lines
10 KiB
LLVM
; Test loop tuning.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-block-placement | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -disable-block-placement \
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; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-Z13
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; Test that strength reduction is applied to addresses with a scale factor,
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; but that indexed addressing can still be used.
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define void @f1(ptr %dest, i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: sllg
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; CHECK: st %r3, 400({{%r[1-5],%r[1-5]}})
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%index = phi i64 [ 0, %entry ], [ %next, %loop ]
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%ptr = getelementptr i32, ptr %dest, i64 %index
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store i32 %a, ptr %ptr
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%next = add i64 %index, 1
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%cmp = icmp ne i64 %next, 100
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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; Test a loop that should be converted into dbr form and then use BRCT.
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define void @f2(ptr %src, ptr %dest) {
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; CHECK-LABEL: f2:
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; CHECK: lhi [[REG:%r[0-5]]], 100
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; CHECK: [[LABEL:\.[^:]*]]:{{.*}} %loop
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; CHECK: brct [[REG]], [[LABEL]]
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%count = phi i32 [ 0, %entry ], [ %next, %loop.next ]
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%next = add i32 %count, 1
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%val = load volatile i32, ptr %src
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %loop.next, label %loop.store
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loop.store:
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%add = add i32 %val, 1
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store volatile i32 %add, ptr %dest
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br label %loop.next
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loop.next:
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%cont = icmp ne i32 %next, 100
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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; Like f2, but for BRCTG.
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define void @f3(ptr %src, ptr %dest) {
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; CHECK-LABEL: f3:
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; CHECK: lghi [[REG:%r[0-5]]], 100
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; CHECK: [[LABEL:\.[^:]*]]:{{.*}} %loop
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; CHECK: brctg [[REG]], [[LABEL]]
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%count = phi i64 [ 0, %entry ], [ %next, %loop.next ]
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%next = add i64 %count, 1
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%val = load volatile i64, ptr %src
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %loop.next, label %loop.store
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loop.store:
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%add = add i64 %val, 1
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store volatile i64 %add, ptr %dest
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br label %loop.next
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loop.next:
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%cont = icmp ne i64 %next, 100
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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; Test a loop with a 64-bit decremented counter in which the 32-bit
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; low part of the counter is used after the decrement. This is an example
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; of a subregister use being the only thing that blocks a conversion to BRCTG.
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define void @f4(ptr %src, ptr %dest, ptr %dest2, i64 %count) {
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; CHECK-LABEL: f4:
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; CHECK: aghi [[REG:%r[0-5]]], -1
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; CHECK: lr [[REG2:%r[0-5]]], [[REG]]
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; CHECK: stg [[REG2]],
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; CHECK: jne {{\..*}}
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%left = phi i64 [ %count, %entry ], [ %next, %loop.next ]
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store volatile i64 %left, ptr %dest2
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%val = load volatile i32, ptr %src
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %loop.next, label %loop.store
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loop.store:
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%add = add i32 %val, 1
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store volatile i32 %add, ptr %dest
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br label %loop.next
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loop.next:
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%next = add i64 %left, -1
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%ext = zext i32 %val to i64
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%shl = shl i64 %ext, 32
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%and = and i64 %next, 4294967295
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%or = or i64 %shl, %and
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store volatile i64 %or, ptr %dest2
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%cont = icmp ne i64 %next, 0
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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; Test that negative offsets are avoided for loads of floating point.
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%s.float = type { float, float, float }
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define void @f5(ptr nocapture %a,
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ptr nocapture readonly %b,
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i32 zeroext %S) {
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; CHECK-Z13-LABEL: f5:
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; CHECK-Z13-NOT: -{{[0-9]+}}(%r
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entry:
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%cmp9 = icmp eq i32 %S, 0
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br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.cond.cleanup.loopexit: ; preds = %for.body
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
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%a1 = getelementptr inbounds %s.float, ptr %b, i64 %indvars.iv, i32 0
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%tmp = load float, ptr %a1, align 4
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%b4 = getelementptr inbounds %s.float, ptr %b, i64 %indvars.iv, i32 1
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%tmp1 = load float, ptr %b4, align 4
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%add = fadd float %tmp, %tmp1
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%c = getelementptr inbounds %s.float, ptr %b, i64 %indvars.iv, i32 2
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%tmp2 = load float, ptr %c, align 4
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%add7 = fadd float %add, %tmp2
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%a10 = getelementptr inbounds %s.float, ptr %a, i64 %indvars.iv, i32 0
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store float %add7, ptr %a10, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %S
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br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
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}
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; Test that negative offsets are avoided for loads of double.
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%s.double = type { double, double, double }
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define void @f6(ptr nocapture %a,
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ptr nocapture readonly %b,
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i32 zeroext %S) {
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; CHECK-Z13-LABEL: f6:
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; CHECK-Z13-NOT: -{{[0-9]+}}(%r
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entry:
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%cmp9 = icmp eq i32 %S, 0
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br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.cond.cleanup.loopexit: ; preds = %for.body
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
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%a1 = getelementptr inbounds %s.double, ptr %b, i64 %indvars.iv, i32 0
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%tmp = load double, ptr %a1, align 4
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%b4 = getelementptr inbounds %s.double, ptr %b, i64 %indvars.iv, i32 1
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%tmp1 = load double, ptr %b4, align 4
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%add = fadd double %tmp, %tmp1
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%c = getelementptr inbounds %s.double, ptr %b, i64 %indvars.iv, i32 2
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%tmp2 = load double, ptr %c, align 4
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%add7 = fadd double %add, %tmp2
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%a10 = getelementptr inbounds %s.double, ptr %a, i64 %indvars.iv, i32 0
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store double %add7, ptr %a10, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %S
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br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
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}
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; Test that negative offsets are avoided for memory accesses of vector type.
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%s.vec = type { <4 x i32>, <4 x i32>, <4 x i32> }
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define void @f7(ptr nocapture %a,
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ptr nocapture readonly %b,
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i32 zeroext %S) {
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; CHECK-Z13-LABEL: f7:
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; CHECK-Z13-NOT: -{{[0-9]+}}(%r
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entry:
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%cmp9 = icmp eq i32 %S, 0
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br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.cond.cleanup.loopexit: ; preds = %for.body
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
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%a1 = getelementptr inbounds %s.vec, ptr %b, i64 %indvars.iv, i32 0
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%tmp = load <4 x i32>, ptr %a1, align 4
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%b4 = getelementptr inbounds %s.vec, ptr %b, i64 %indvars.iv, i32 1
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%tmp1 = load <4 x i32>, ptr %b4, align 4
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%add = add <4 x i32> %tmp1, %tmp
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%c = getelementptr inbounds %s.vec, ptr %b, i64 %indvars.iv, i32 2
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%tmp2 = load <4 x i32>, ptr %c, align 4
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%add7 = add <4 x i32> %add, %tmp2
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%a10 = getelementptr inbounds %s.vec, ptr %a, i64 %indvars.iv, i32 0
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store <4 x i32> %add7, ptr %a10, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %S
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br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
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}
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; Test that a memcpy loop does not get a lot of lays before each mvc (D12 and no index-reg).
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%0 = type { %1, ptr }
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%1 = type { ptr, ptr }
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%2 = type <{ %3, i32, [4 x i8] }>
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%3 = type { ptr, ptr, ptr }
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declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #0
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define void @f8() {
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; CHECK-Z13-LABEL: f8:
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; CHECK-Z13: mvc
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; CHECK-Z13-NEXT: mvc
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; CHECK-Z13-NEXT: mvc
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; CHECK-Z13-NEXT: mvc
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bb:
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%tmp = load ptr, ptr undef, align 8
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br i1 undef, label %bb2, label %bb1
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bb1: ; preds = %bb
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br label %bb2
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bb2: ; preds = %bb1, %bb
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%tmp3 = phi ptr [ %tmp, %bb ], [ undef, %bb1 ]
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%tmp4 = phi ptr [ undef, %bb ], [ undef, %bb1 ]
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br label %bb5
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bb5: ; preds = %bb5, %bb2
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%tmp6 = phi ptr [ %tmp21, %bb5 ], [ %tmp3, %bb2 ]
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%tmp7 = phi ptr [ %tmp20, %bb5 ], [ %tmp4, %bb2 ]
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%tmp8 = getelementptr inbounds %0, ptr %tmp7, i64 -1
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%tmp9 = getelementptr inbounds %0, ptr %tmp6, i64 -1
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tail call void @llvm.memcpy.p0.p0.i64(ptr align 8 %tmp9, ptr align 8 %tmp8, i64 24, i1 false)
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%tmp12 = getelementptr inbounds %0, ptr %tmp7, i64 -2
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%tmp13 = getelementptr inbounds %0, ptr %tmp6, i64 -2
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tail call void @llvm.memcpy.p0.p0.i64(ptr align 8 %tmp13, ptr align 8 %tmp12, i64 24, i1 false)
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%tmp16 = getelementptr inbounds %0, ptr %tmp7, i64 -3
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%tmp17 = getelementptr inbounds %0, ptr %tmp6, i64 -3
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tail call void @llvm.memcpy.p0.p0.i64(ptr align 8 %tmp17, ptr align 8 %tmp16, i64 24, i1 false)
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%tmp20 = getelementptr inbounds %0, ptr %tmp7, i64 -4
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%tmp21 = getelementptr inbounds %0, ptr %tmp6, i64 -4
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tail call void @llvm.memcpy.p0.p0.i64(ptr align 8 %tmp21, ptr align 8 %tmp20, i64 24, i1 false)
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br label %bb5
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}
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; Test that a chsi does not need an aghik inside the loop (no index reg)
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define void @f9() {
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; CHECK-Z13-LABEL: f9:
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; CHECK-Z13: # =>This Inner Loop Header: Depth=1
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; CHECK-Z13-NOT: aghik
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; CHECK-Z13: chsi
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entry:
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br label %for.body.i63
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for.body.i63: ; preds = %for.inc.i, %entry
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%indvars.iv155.i = phi i64 [ 0, %entry ], [ %indvars.iv.next156.i.3, %for.inc.i ]
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%arrayidx.i62 = getelementptr inbounds i32, ptr undef, i64 %indvars.iv155.i
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%tmp = load i32, ptr %arrayidx.i62, align 4
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%cmp9.i = icmp eq i32 %tmp, 0
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br i1 %cmp9.i, label %for.inc.i, label %if.then10.i
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if.then10.i: ; preds = %for.body.i63
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unreachable
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for.inc.i: ; preds = %for.body.i63
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%indvars.iv.next156.i = or i64 %indvars.iv155.i, 1
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%arrayidx.i62.1 = getelementptr inbounds i32, ptr undef, i64 %indvars.iv.next156.i
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%tmp1 = load i32, ptr %arrayidx.i62.1, align 4
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%indvars.iv.next156.i.3 = add nsw i64 %indvars.iv155.i, 4
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br label %for.body.i63
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}
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