Luke Lau 02bb33c3ce [RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores ...

As noted by @reames, we should be checking that the memory access is aligned to
the element size (or the unaligned vector memory access feature is enabled)
before lowering vlseg/vsseg intrinsics via the interleaved access pass.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D154536

2023-07-07 15:34:24 +01:00

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