245e3dd948
Avoid copying MCInstrDesc instances because a future patch will change them to find their implicit operands and operand info array based on their own "this" pointer, so it will only work for MCInstrDescs in the TargetInsts table, not for a copy of an MCInstrDesc at a different address. Differential Revision: https://reviews.llvm.org/D142214
123 lines
4.5 KiB
C++
123 lines
4.5 KiB
C++
//===-- SPIRVMCCodeEmitter.cpp - Emit SPIR-V machine code -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SPIRVMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SPIRVMCTargetDesc.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "spirv-mccodeemitter"
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namespace {
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class SPIRVMCCodeEmitter : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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public:
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SPIRVMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {}
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SPIRVMCCodeEmitter(const SPIRVMCCodeEmitter &) = delete;
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void operator=(const SPIRVMCCodeEmitter &) = delete;
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~SPIRVMCCodeEmitter() override = default;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createSPIRVMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx) {
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return new SPIRVMCCodeEmitter(MCII);
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}
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using EndianWriter = support::endian::Writer;
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// Check if the instruction has a type argument for operand 1, and defines an ID
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// output register in operand 0. If so, we need to swap operands 0 and 1 so the
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// type comes first in the output, despide coming second in the MCInst.
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static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
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const MCInstrDesc &MCDesc = MII.get(MI.getOpcode());
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// If we define an output, and have at least one other argument.
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if (MCDesc.getNumDefs() == 1 && MCDesc.getNumOperands() >= 2) {
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// Check if we define an ID, and take a type as operand 1.
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auto &DefOpInfo = MCDesc.operands()[0];
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auto &FirstArgOpInfo = MCDesc.operands()[1];
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return (DefOpInfo.RegClass == SPIRV::IDRegClassID ||
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DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) &&
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FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
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}
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return false;
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}
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static void emitOperand(const MCOperand &Op, EndianWriter &OSE) {
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if (Op.isReg()) {
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// Emit the id index starting at 1 (0 is an invalid index).
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OSE.write<uint32_t>(Register::virtReg2Index(Op.getReg()) + 1);
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} else if (Op.isImm()) {
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OSE.write<uint32_t>(Op.getImm());
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} else {
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llvm_unreachable("Unexpected operand type in VReg");
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}
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}
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// Emit the type in operand 1 before the ID in operand 0 it defines, and all
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// remaining operands in the order they come naturally.
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static void emitTypedInstrOperands(const MCInst &MI, EndianWriter &OSE) {
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unsigned NumOps = MI.getNumOperands();
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emitOperand(MI.getOperand(1), OSE);
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emitOperand(MI.getOperand(0), OSE);
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for (unsigned i = 2; i < NumOps; ++i)
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emitOperand(MI.getOperand(i), OSE);
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}
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// Emit operands in the order they come naturally.
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static void emitUntypedInstrOperands(const MCInst &MI, EndianWriter &OSE) {
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for (const auto &Op : MI)
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emitOperand(Op, OSE);
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}
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void SPIRVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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EndianWriter OSE(OS, support::little);
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// Encode the first 32 SPIR-V bytes with the number of args and the opcode.
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const uint64_t OpCode = getBinaryCodeForInstr(MI, Fixups, STI);
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const uint32_t NumWords = MI.getNumOperands() + 1;
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const uint32_t FirstWord = (NumWords << 16) | OpCode;
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OSE.write<uint32_t>(FirstWord);
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// Emit the instruction arguments (emitting the output type first if present).
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if (hasType(MI, MCII))
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emitTypedInstrOperands(MI, OSE);
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else
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emitUntypedInstrOperands(MI, OSE);
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}
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#include "SPIRVGenMCCodeEmitter.inc"
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