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clang-p2996/llvm/test/CodeGen/RISCV/rvv
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Luke Lau b5bcd4f60b [RISCV] Add VL nodes and VP patterns for unary zvbb instructions 
This follows the pattern of lowering VP nodes to equivalent
RISCVISD::*_VL nodes. The nodes are modelled after the VP ISD nodes rather
than the actual zvbb instructions, and I've included a merge operand to be
consistent with the underlying pseudos that were recently refactored.

I've defined the nodes in RISCVInstrInfoVVLpatterns.td as the nodes aren't Zvk
specific, but the patterns are in RISCVInstrInfoZvk.td.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155229
2023-07-17 09:17:58 +01:00
..
abs-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
abs-vp.ll
[VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp.abs/ctlz/cttz.
2023-02-23 13:58:21 +08:00
access-fixed-objects-by-rvv.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
active_lane_mask.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
addi-rvv-stack-object.mir
…
addi-scalable-offset.mir
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
aliases.mir
…
alloca-load-store-scalable-struct.ll
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
allocate-lmul-2-4-8.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
allone-masked-to-unmasked.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
bitreverse-sdnode.ll
[RISCV] Add initial SDNode patterns for unary zvbb instructions
2023-07-13 19:39:04 +01:00
bitreverse-vp.ll
[RISCV] Add VL nodes and VP patterns for unary zvbb instructions
2023-07-17 09:17:58 +01:00
bswap-sdnode.ll
[RISCV] Add initial SDNode patterns for unary zvbb instructions
2023-07-13 19:39:04 +01:00
bswap-vp.ll
[RISCV] Add VL nodes and VP patterns for unary zvbb instructions
2023-07-17 09:17:58 +01:00
calling-conv-fastcc.ll
[RISCV] Make all vector binops use the _TU pseudo form
2023-06-16 16:28:19 -07:00
calling-conv.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
ceil-vp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
cmp-folds.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
combine-sats.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
combine-splats.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
combine-store.ll
[RISCV] Implement storeOfVectorConstantIsCheap hook to prevent store merging at VL=2
2023-05-17 11:13:57 -07:00
combine-vmv.ll
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
common-shuffle-patterns.ll
[RISCV] Use a smaller VL when interleaving fixed vectors
2023-02-21 09:46:23 +00:00
commuted-op-indices-regression.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
constant-folding-crash.ll
[RISCV] Promote i1 shuffles to i8 shuffles.
2023-05-04 19:44:43 -07:00
constant-folding.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ctlz-sdnode.ll
[RISCV] Add initial SDNode patterns for unary zvbb instructions
2023-07-13 19:39:04 +01:00
ctlz-vp.ll
[RISCV] Add VL nodes and VP patterns for unary zvbb instructions
2023-07-17 09:17:58 +01:00
ctpop-sdnode.ll
[RISCV] Add initial SDNode patterns for unary zvbb instructions
2023-07-13 19:39:04 +01:00
ctpop-vp.ll
[RISCV] Add VL nodes and VP patterns for unary zvbb instructions
2023-07-17 09:17:58 +01:00
cttz-sdnode.ll
[RISCV] Add initial SDNode patterns for unary zvbb instructions
2023-07-13 19:39:04 +01:00
cttz-vp.ll
[RISCV] Add VL nodes and VP patterns for unary zvbb instructions
2023-07-17 09:17:58 +01:00
debug-info-rvv-dbg-value.mir
…
double-round-conv.ll
[RISCV] Add VFCVT pseudos with no mask
2023-07-05 17:28:43 +01:00
emergency-slot.mir
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
expand-no-v.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
extload-truncstore.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
extract-subvector.ll
[RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion
2023-06-12 10:01:39 -07:00
extractelt-fp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
extractelt-i1.ll
[RISCV] Canonicalize towards vmerge w/passthrough representation
2023-06-13 16:26:37 -07:00
extractelt-int-rv32.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
extractelt-int-rv64.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fceil-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fceil-sdnode.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
ffloor-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
ffloor-sdnode.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fixed-vectors-abs-vp.ll
[RISCV] Fix unmasked vp_abs select.
2023-05-30 09:57:40 +08:00
fixed-vectors-abs.ll
[LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops
2023-06-12 10:21:04 +01:00
fixed-vectors-bitcast-large-vector.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-bitcast.ll
[RISCV] Use vslide1down lowering for two element non-constant build_vectors
2023-05-03 07:35:23 -07:00
fixed-vectors-bitreverse-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-bitreverse.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-bswap-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-bswap.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-calling-conv-fastcc.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-calling-conv.ll
[RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion
2023-06-12 10:01:39 -07:00
fixed-vectors-ceil-vp.ll
[RISCV] Fix selection for some unmasked vp SDNode.
2023-05-31 09:54:44 +08:00
fixed-vectors-ctlz-vp.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
fixed-vectors-ctlz.ll
[RISCV] Add VFCVT pseudos with no mask
2023-07-05 17:28:43 +01:00
fixed-vectors-ctpop-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-ctpop.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-cttz-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-cttz.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-deinterleave-load.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-elen.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fixed-vectors-emergency-slot.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-extload-truncstore.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-extract-i1.ll
Revert "[RISCV] Fix extract_vector_elt on i1 at idx 0 being inverted"
2023-05-10 15:07:32 -07:00
fixed-vectors-extract-subvector.ll
[RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion
2023-06-12 10:01:39 -07:00
fixed-vectors-extract.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-fceil-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fixed-vectors-ffloor-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fixed-vectors-floor-vp.ll
[RISCV] Fix selection for some unmasked vp SDNode.
2023-05-31 09:54:44 +08:00
fixed-vectors-fmf.ll
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
fixed-vectors-fnearbyint-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fixed-vectors-fp2i-sat.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-fp2i.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-fp-bitcast.ll
[RISCV] Optimize i64 insertelt on RV32.
2022-10-28 10:23:19 -07:00
fixed-vectors-fp-buildvec.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-fp-conv.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-fp-interleave.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-fp-setcc.ll
[RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion
2023-06-12 10:01:39 -07:00
fixed-vectors-fp-shuffles.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-fp-splat.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-fp-vrgather.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-fp.ll
[LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops
2023-06-12 10:21:04 +01:00
fixed-vectors-fpext-vp.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-fptosi-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-fptosi-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-fptoui-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-fptoui-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-fptrunc-vp.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-fround-costrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fixed-vectors-fround.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fixed-vectors-froundeven-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fixed-vectors-froundeven.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fixed-vectors-fshr-fshl-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-ftrunc-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fixed-vectors-i2fp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-insert-i1.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-insert-subvector-shuffle.ll
[RISCV] Add test cases for insert subvector shuffles for fixed vectors
2023-06-28 22:52:48 +01:00
fixed-vectors-insert-subvector.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-insert.ll
[DAGCombine] Fold (store (insert_elt (load p)) x p) -> (store x)
2023-06-28 22:45:04 +01:00
fixed-vectors-int-buildvec.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-int-exttrunc.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-int-interleave.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-int-setcc.ll
[RISCV] Prefer vmsle.vi vX, vY, -1 over vslt.vx vX, vY, x0.
2023-04-24 11:45:27 -07:00
fixed-vectors-int-shuffles.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-int-splat.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-int-vrgather.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-int.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-interleave-store.ll
[RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores
2023-07-07 15:34:24 +01:00
fixed-vectors-interleaved-access-zve32x.ll
[RISCV] Lower scalar_to_vector
2023-04-06 17:39:19 +01:00
fixed-vectors-interleaved-access.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-inttoptr-ptrtoint.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-load-store.ll
[RISCV] Don't scalarize vector stores if volatile
2023-05-26 09:34:34 +01:00
fixed-vectors-load.ll
[LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops
2023-06-12 10:21:04 +01:00
fixed-vectors-marith-vp.ll
[RISCV] Cleanup some vector tests. NFC
2022-10-06 10:51:39 -07:00
fixed-vectors-mask-buildvec.ll
[RISCV] Use a build_vector instead of a chain insert_vector_elts for vXi1 build_vector lowreing.
2023-06-21 08:57:46 -07:00
fixed-vectors-mask-load-store.ll
[RISCV] Scalarize small fixed vector copies < XLEN
2023-05-24 10:25:40 +01:00
fixed-vectors-mask-logic.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-mask-splat.ll
[RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion
2023-06-12 10:01:39 -07:00
fixed-vectors-masked-gather.ll
[RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl
2023-07-08 08:03:15 +08:00
fixed-vectors-masked-load-fp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fixed-vectors-masked-load-int.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-masked-scatter.ll
[RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl
2023-07-08 08:03:15 +08:00
fixed-vectors-masked-store-fp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fixed-vectors-masked-store-int.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-nearbyint-vp.ll
[RISCV] Fix selection for some unmasked vp SDNode.
2023-05-31 09:54:44 +08:00
fixed-vectors-peephole-vmerge-vops.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-reduction-fp-vp.ll
[RISCV][RISCVISelLowering] Add tail agnostic policy operand to VECREDUCE instructions
2023-03-25 02:42:13 -07:00
fixed-vectors-reduction-fp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-reduction-int-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for VID
2023-06-27 09:12:00 -07:00
fixed-vectors-reduction-int.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-reduction-mask-vp.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
fixed-vectors-rint-vp.ll
[RISCV] Fix selection for some unmasked vp SDNode.
2023-05-31 09:54:44 +08:00
fixed-vectors-round-vp.ll
[RISCV] Fix selection for some unmasked vp SDNode.
2023-05-31 09:54:44 +08:00
fixed-vectors-roundeven-vp.ll
[RISCV] Fix selection for some unmasked vp SDNode.
2023-05-31 09:54:44 +08:00
fixed-vectors-roundtozero-vp.ll
[RISCV] Fix selection for some unmasked vp SDNode.
2023-05-31 09:54:44 +08:00
fixed-vectors-segN-load.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-segN-store.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-select-fp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-select-int.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-setcc-fp-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-setcc-int-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-setcc-int-vp.ll
[RISCV] Use tail agnostic policy more often when lowering insert_subvector
2023-04-06 10:31:45 +01:00
fixed-vectors-sext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-sext-vp.ll
Recommit "[SelectionDAG][RISCV] Add very basic PromoteIntegerResult/Op support for VP_SIGN/ZERO_EXTEND."
2023-06-15 12:03:25 -07:00
fixed-vectors-shuffle-extract-subvector.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-shuffle-reverse.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-shuffle-transpose.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-shuffle-vslide1down.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-shuffle-vslide1up.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-shufflevector-vnsrl.ll
[RISCV] Use a build_vector instead of a chain insert_vector_elts for vXi1 build_vector lowreing.
2023-06-21 08:57:46 -07:00
fixed-vectors-sitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-sitofp-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-stepvector.ll
[RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable
2022-12-13 07:54:46 -08:00
fixed-vectors-store-merge-crash.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-store.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-strided-load-combine.ll
[LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops
2023-06-12 10:21:04 +01:00
fixed-vectors-strided-load-store-asm.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-strided-load-store-negative.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-strided-load-store.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-strided-vpload.ll
[RISCV][NFC] Use common prefix to simplify test.
2023-06-02 12:16:03 +08:00
fixed-vectors-strided-vpstore.ll
[RISCV][NFC] Use common prefix to simplify test.
2023-06-02 12:16:03 +08:00
fixed-vectors-trunc-vp-mask.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-trunc-vp.ll
[RISCV] Rename prefix fixed-vector to fixed-vectors to be the same with other testcases. NFC.
2023-07-07 13:04:00 +08:00
fixed-vectors-uitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-uitofp-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-unaligned.ll
[RISCV] Custom lower fixed vector undef to scalable undef
2023-06-21 17:14:57 +01:00
fixed-vectors-vadd-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vadd-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-vand-vp.ll
[RISCV] Use a build_vector instead of a chain insert_vector_elts for vXi1 build_vector lowreing.
2023-06-21 08:57:46 -07:00
fixed-vectors-vcopysign-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-vdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vdivu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfabs-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vfadd-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
fixed-vectors-vfadd-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfclass.ll
[RISCV] Improve selection for vector fpclass.
2023-06-06 10:24:24 +08:00
fixed-vectors-vfcmp-constrained-sdnode.ll
[RISCV] Support vector strict_fsetcc/fsetccs.
2023-04-14 09:10:41 +08:00
fixed-vectors-vfcmps-constrained-sdnode.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fixed-vectors-vfdiv-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
fixed-vectors-vfdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfma-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-vfmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmadd-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
fixed-vectors-vfmax-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-vfmax.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmin-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-vfmin.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmsac-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmsub-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
fixed-vectors-vfmul-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
fixed-vectors-vfmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfmuladd-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-vfneg-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vfnmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfnmadd-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
fixed-vectors-vfnmsac-vp.ll
[RISCV] Use fixed vector types in fixed-vectors-vfnmsac-vp.ll. NFC
2022-10-06 11:02:13 -07:00
fixed-vectors-vfnmsub-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
fixed-vectors-vfpext-constrained-sdnode.ll
[IR][DAG][RISCV] Allow scalable vector ISD::STRICT_FP_EXTEND and RISC-V supports for vector ISD::STRICT_FP_EXTEND.
2023-03-09 17:37:59 +08:00
fixed-vectors-vfptoi-constrained-sdnode.ll
[RISCV] Regenerate missing test checks
2023-05-26 07:33:28 +01:00
fixed-vectors-vfptrunc-constrained-sdnode.ll
[DAG][RISCV] Allow scalable vector ISD::STRICT_FP_ROUND and support vector ISD::STRICT_FP_ROUND for RISC-V.
2023-03-30 08:20:02 +08:00
fixed-vectors-vfrdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfsqrt-constrained-sdnode.ll
[RISCV] Support vector type strict_fsqrt.
2023-03-27 14:02:22 +08:00
fixed-vectors-vfsqrt-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vfsub-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
fixed-vectors-vfsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfwadd.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vfwmacc.ll
[RISCV] Add test cases for forming vfwmacc when widening from f16 to f64. NFC
2023-05-14 22:35:39 -07:00
fixed-vectors-vfwmul.ll
[RISCV] Allow FWMUL formation for an FP extend used twice by the same multiply.
2023-05-30 15:08:08 -07:00
fixed-vectors-vfwsub.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vitofp-constrained-sdnode.ll
[RISCV] Support vector type strict_[su]int_to_fp and strict_fp_to_[su]int.
2023-04-06 10:09:44 +08:00
fixed-vectors-vmacc-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
fixed-vectors-vmax-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vmaxu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vmin-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vminu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vmul-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vnmsac-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
fixed-vectors-vnsra-vnsrl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vpgather.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
fixed-vectors-vpload.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vpmerge.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vpscatter.ll
[RISCV] Match shl_vl (ext_vl v, splat 1) to vwadd_vl
2023-07-08 08:03:15 +08:00
fixed-vectors-vpstore.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vreductions-mask.ll
Revert "[RISCV] Fix extract_vector_elt on i1 at idx 0 being inverted"
2023-05-10 15:07:32 -07:00
fixed-vectors-vrem-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vremu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vsadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vsaddu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vscale-range.ll
[RISCV] Add support for the vscale_range attribute.
2023-01-06 08:20:37 -08:00
fixed-vectors-vselect-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
fixed-vectors-vselect.ll
[LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops
2023-06-12 10:21:04 +01:00
fixed-vectors-vshl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vsra-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vsrl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vssub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vssubu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vsub-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vw-web-simplification.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwadd.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwaddu.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwmacc.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwmaccsu.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwmaccu.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwmaccus.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwmul.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwmulsu.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwmulu.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwsub.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vwsubu.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixed-vectors-vxor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-zext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-zext-vp.ll
Recommit "[SelectionDAG][RISCV] Add very basic PromoteIntegerResult/Op support for VP_SIGN/ZERO_EXTEND."
2023-06-15 12:03:25 -07:00
float-round-conv.ll
[RISCV] Add VFCVT pseudos with no mask
2023-07-05 17:28:43 +01:00
floor-vp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fnearbyint-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fnearbyint-sdnode.ll
[RISCV] Customed lower vector nearbyint and rint in RISC-V.
2023-04-19 11:07:23 +08:00
fold-binary-reduce.ll
[RISCV] Remove one use restriction on the scalar from combineBinOpToReduce.
2023-04-25 21:10:58 -07:00
fold-scalar-load-crash.ll
[RISCV] Don't fold RISCVISD::VMV_V_X_VL series node and scalar load to vector load when scalar load is update load
2023-07-11 15:56:31 +08:00
fold-vector-cmp.ll
Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
2023-05-10 11:51:51 -07:00
fold-vp-fadd-and-vp-fmul.ll
[RISCV] Use mask agnostic policy for masked RISCVISD::VFMADD_VL patterns.
2023-05-15 23:16:38 -07:00
fold-vp-fsub-and-vp-fmul.ll
[RISCV] Use mask agnostic policy for masked RISCVISD::VFMADD_VL patterns.
2023-05-15 23:16:38 -07:00
fpclamptosat_vec.ll
[RISCV] Custom lower FP_TO_FP16 and FP16_TO_FP to correct ABI of of libcall
2023-06-30 16:41:49 +01:00
fptosi-sat.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
fptoui-sat.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
frameindex-addr.ll
…
frint-sdnode.ll
[RISCV] Customed lower vector nearbyint and rint in RISC-V.
2023-04-19 11:07:23 +08:00
fround-costrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
fround-sdnode.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
froundeven-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
froundeven-sdnode.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fshr-fshl-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fshr-fshl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ftrunc-constrained-sdnode.ll
[RISCV] Support vector strict rounding operations.
2023-04-27 11:35:34 +08:00
ftrunc-sdnode.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
get_vector_length.ll
[RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.
2023-06-05 15:02:11 -07:00
get-vlen-debugloc.mir
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
half-round-conv.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
implicit-def-copy.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
inline-asm.ll
…
insert-subvector.ll
[RISCV] Canonicalize towards vmerge w/passthrough representation
2023-06-13 16:26:37 -07:00
insertelt-fp.ll
[RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x
2023-05-31 18:18:44 +01:00
insertelt-i1.ll
[RISCV] Canonicalize towards vmerge w/passthrough representation
2023-06-13 16:26:37 -07:00
insertelt-int-rv32.ll
[RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x
2023-05-31 18:18:44 +01:00
insertelt-int-rv64.ll
[RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x
2023-05-31 18:18:44 +01:00
interleave-crash.ll
[RISCV] Use a smaller VL when interleaving fixed vectors
2023-02-21 09:46:23 +00:00
large-rvv-stack-size.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
legalize-load-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
legalize-scalable-vectortype.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
legalize-store-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-8.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-16.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
localvar.ll
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
marith-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mask-exts-truncs-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mask-exts-truncs-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mask-reg-alloc.mir
[RISCV] Remove legacy TA/TU pseudo distinction of vmerge and carry-in arithmetic operations [NFC[
2023-07-12 15:31:02 -07:00
masked-load-fp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
masked-load-int.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
masked-store-fp.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
masked-store-int.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
masked-tama.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
masked-tamu.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
masked-tuma.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
masked-tumu.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
masked-vslide1down-rv32.ll
[RISCV] Make vsetvli intrinsics default to MA.
2023-02-13 10:39:55 -08:00
memory-args.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mgather-sdnode.ll
[RISCV] Narrow types of index operand matched pattern (shl (zext), C).
2023-07-14 15:45:44 +08:00
mscatter-combine.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mscatter-sdnode.ll
[RISCV] Narrow types of index operand matched pattern (shl (zext), C).
2023-07-14 15:45:44 +08:00
mutate-prior-vsetvli-avl.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
named-vector-shuffle-reverse.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
narrow-shift-extend.ll
[RISCV] Narrow types of index operand matched pattern (shl (zext), C).
2023-07-14 15:45:44 +08:00
nearbyint-vp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
no-reserved-frame.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pass-fast-math-flags-sdnode.ll
[3/8][RISCV] Add rounding mode control variant for vfmul, vfdiv, vfrdiv, vfwmul
2023-07-13 00:43:54 -07:00
pr52475.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr61561.ll
[SelectionDAG][RISCV] Remove code for handling too small shift type from SimplifyDemandedBits.
2023-03-21 11:08:19 -07:00
pr63459.ll
[RISCV][SelectionDAGBuilder] Fix an implicit scalable TypeSize to fixed size conversion in getUniformBase.
2023-06-26 11:56:17 -07:00
pr63596.ll
[RISCV] Custom lower FP_TO_FP16 and FP16_TO_FP to correct ABI of of libcall
2023-06-30 16:41:49 +01:00
reg-alloc-reserve-bp.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
reg-coalescing.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
regalloc-fast-crash.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
rint-vp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
round-vp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
roundeven-vp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
roundtozero-vp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
rv32-spill-vector-csr.ll
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
rv32-spill-vector.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
rv32-spill-zvlsseg.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
rv64-spill-vector-csr.ll
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
rv64-spill-vector.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
rv64-spill-zvlsseg.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
rvv-args-by-mem.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
rvv-framelayout.ll
…
rvv-out-arguments.ll
[RISCV] Make vsetvli intrinsics default to MA.
2023-02-13 10:39:55 -08:00
rvv-peephole-vmerge-masked-vops.ll
[1/8][RISCV] Add rounding mode control variant for vfsub, vfrsub
2023-07-13 00:35:36 -07:00
rvv-peephole-vmerge-vops-mir.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
rvv-peephole-vmerge-vops.ll
[RISCV] Don't fold vmerge into ops if fp exception can be raised
2023-07-13 11:42:23 +01:00
rvv-stack-align.mir
…
rvv-vmerge-to-vmv.ll
[RISCV] Use tail undisturbed vmv.v.v instead of vadd.vi with 0 for vp.merge with all ones mask.
2023-06-12 10:27:08 -07:00
rvv-vscale.i32.ll
…
rvv-vscale.i64.ll
…
saddo-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
scalable-vector-struct.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
scalar-stack-align.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
select-fp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
select-int.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
select-sra.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
setcc-fp-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
setcc-fp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
setcc-int-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
setcc-int-vp.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
setcc-integer.ll
[RISCV] Prefer vmsle.vi vX, vY, -1 over vslt.vx vX, vY, x0.
2023-04-24 11:45:27 -07:00
shuffle-reverse.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
sink-splat-operands-i1.ll
[RISCV] Don't sink i1 vectors in shouldSinkOperands.
2023-07-06 20:36:55 -07:00
sink-splat-operands.ll
[RISCV] Use mask agnostic policy for masked RISCVISD::VFMADD_VL patterns.
2023-05-15 23:16:38 -07:00
smulo-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
splat-vector-split-i64-vl-sdnode.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
splat-vectors.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
splats-with-mixed-vl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
sshl_sat_vec.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
stack-coloring-scalablevec.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
stepvector.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
strided-load-store-intrinsics.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
strided-load-store.ll
[RISCVGatherScatterLowering] Use InstSimplifyFolder
2023-05-12 17:33:07 -07:00
strided-vpload.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
strided-vpstore.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
subregister-undef-early-clobber.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
tail-agnostic-impdef-copy.mir
…
umulo-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
unaligned-loads-stores.ll
[RISCV] Introduce unaligned-vector-mem feature
2023-04-28 08:28:08 -07:00
undef-earlyclobber-chain.ll
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
undef-vp-ops.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
unmasked-ta.ll
[8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
2023-07-13 00:55:10 -07:00
unmasked-tu.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
urem-seteq-vec.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ushl_sat_vec.ll
[LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling.
2022-10-27 09:09:36 -07:00
vaadd.ll
[3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub
2023-06-20 11:08:09 -07:00
vaaddu.ll
[3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub
2023-06-20 11:08:09 -07:00
vadc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vadd-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vadd-vp-mask.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vadd-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vadd.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
vand-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vand-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vand.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
variant-cc.ll
[RISCV] Emit .variant_cc directives for vector function calls.
2022-12-16 13:51:39 +08:00
vasub.ll
[3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub
2023-06-20 11:08:09 -07:00
vasubu.ll
[3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub
2023-06-20 11:08:09 -07:00
vcompress.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vcopysign-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vcpop.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vdiv-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vdiv-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vdiv.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vdivu-sdnode.ll
[DAGCombiner] Make it so that udiv can be folded with (select c, NonZero, 1)
2023-07-12 17:17:53 -05:00
vdivu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vdivu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vec3-setcc-crash.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vector-deinterleave-fixed.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vector-deinterleave-load.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vector-deinterleave.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vector-interleave-fixed.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
vector-interleave-store.ll
[RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores
2023-07-07 15:34:24 +01:00
vector-interleave.ll
[RISCV] Remove mask from vrgatherei16 in lowerVECTOR_INTERLEAVE.
2023-06-20 09:36:38 -07:00
vector-splice.ll
[RISCV] Canonicalize towards vmerge w/passthrough representation
2023-06-13 16:26:37 -07:00
vexts-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfabs-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfabs-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfadd-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
vfadd-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vfadd-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfadd.ll
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
vfclass-sdnode.ll
[RISCV] Improve selection for vector fpclass.
2023-06-06 10:24:24 +08:00
vfclass.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcmp-constrained-sdnode.ll
[RISCV] Support vector strict_fsetcc/fsetccs.
2023-04-14 09:10:41 +08:00
vfcmps-constrained-sdnode.ll
[RISCV] Support vector strict_fsetcc/fsetccs.
2023-04-14 09:10:41 +08:00
vfcopysign-sdnode.ll
[DAG] Restrict (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) combine
2023-04-18 10:37:18 -07:00
vfcvt-f-x.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfcvt-f-xu.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfcvt-rtz-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcvt-rtz-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcvt-x-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfcvt-xu-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfdiv-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
vfdiv-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vfdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfdiv.ll
[3/8][RISCV] Add rounding mode control variant for vfmul, vfdiv, vfrdiv, vfwmul
2023-07-13 00:43:54 -07:00
vfirst.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfma-vp-combine.ll
[DAGCombiner] Use generalized pattern matcher in visitFMA to support vp.fma.
2023-06-08 09:40:21 +08:00
vfma-vp.ll
[RISCV] Remove overly restrictive assert from negateFMAOpcode.
2023-06-06 18:55:58 -07:00
vfmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmacc.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfmadd-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
vfmadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmadd.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfmax-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmax-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfmax.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmerge.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmin-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmin-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfmin.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmsac-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmsac.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfmsub-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
vfmsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmsub.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfmul-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
vfmul-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vfmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfmul.ll
[3/8][RISCV] Add rounding mode control variant for vfmul, vfdiv, vfrdiv, vfwmul
2023-07-13 00:43:54 -07:00
vfmuladd-vp.ll
[RISCV] Use mask agnostic policy for masked RISCVISD::VFMADD_VL patterns.
2023-05-15 23:16:38 -07:00
vfmv.f.s.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmv.s.f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmv.v.f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-f-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfncvt-f-x.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfncvt-f-xu.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfncvt-rod-f-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-rtz-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-rtz-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-x-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfncvt-xu-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfneg-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfneg-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfnmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmacc.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfnmadd-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
vfnmadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmadd.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfnmsac-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmsac.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfnmsub-constrained-sdnode.ll
[RISCV] Support vector type strict_fma.
2023-03-28 09:01:46 +08:00
vfnmsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmsub.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vfpext-constrained-sdnode.ll
[IR][DAG][RISCV] Allow scalable vector ISD::STRICT_FP_EXTEND and RISC-V supports for vector ISD::STRICT_FP_EXTEND.
2023-03-09 17:37:59 +08:00
vfpext-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfpext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfptoi-constrained-sdnode.ll
[RISCV] Support vector type strict_[su]int_to_fp and strict_fp_to_[su]int.
2023-04-06 10:09:44 +08:00
vfptoi-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfptosi-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vfptosi-vp.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vfptoui-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vfptoui-vp.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vfptrunc-constrained-sdnode.ll
[DAG][RISCV] Allow scalable vector ISD::STRICT_FP_ROUND and support vector ISD::STRICT_FP_ROUND for RISC-V.
2023-03-30 08:20:02 +08:00
vfptrunc-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfptrunc-vp.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vfrdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfrdiv.ll
[3/8][RISCV] Add rounding mode control variant for vfmul, vfdiv, vfrdiv, vfwmul
2023-07-13 00:43:54 -07:00
vfrec7.ll
[6/8][RISCV] Add rounding mode control variant for vfsqrt, vfrec7
2023-07-13 00:51:51 -07:00
vfredmax.ll
[RISCV][RISCVISelLowering] Add tail agnostic policy operand to VECREDUCE instructions
2023-03-25 02:42:13 -07:00
vfredmin.ll
[RISCV][RISCVISelLowering] Add tail agnostic policy operand to VECREDUCE instructions
2023-03-25 02:42:13 -07:00
vfredosum.ll
[8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
2023-07-13 00:55:10 -07:00
vfredusum.ll
[8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
2023-07-13 00:55:10 -07:00
vfrsqrt7.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfrsub.ll
[1/8][RISCV] Add rounding mode control variant for vfsub, vfrsub
2023-07-13 00:35:36 -07:00
vfsgnj.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsgnjn.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsgnjx.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfslide1down.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfslide1up.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsqrt-constrained-sdnode.ll
[RISCV] Support vector type strict_fsqrt.
2023-03-27 14:02:22 +08:00
vfsqrt-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsqrt-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfsqrt.ll
[6/8][RISCV] Add rounding mode control variant for vfsqrt, vfrec7
2023-07-13 00:51:51 -07:00
vfsub-constrained-sdnode.ll
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
vfsub-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vfsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfsub.ll
[1/8][RISCV] Add rounding mode control variant for vfsub, vfrsub
2023-07-13 00:35:36 -07:00
vfwadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwadd-vp.ll
[RISCV] Add RISCVISD nodes for vfwadd/vfwsub.
2023-06-05 14:12:47 -07:00
vfwadd.ll
[2/8][RISCV] Add rounding mode control variant for vfwadd, vfwsub
2023-07-13 00:42:00 -07:00
vfwadd.w.ll
[2/8][RISCV] Add rounding mode control variant for vfwadd, vfwsub
2023-07-13 00:42:00 -07:00
vfwcvt-f-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfwcvt-f-x.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfwcvt-f-xu.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfwcvt-rtz-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-rtz-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-x-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfwcvt-xu-f.ll
[7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer
2023-07-13 00:54:07 -07:00
vfwmacc-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwmacc-vp.ll
[RISCV] Teach performCombineVMergeAndVOps to handle instructions FMA instructions.
2023-05-29 19:44:43 -07:00
vfwmacc.ll
[5/8][RISCV] Add rounding mode control variant for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac
2023-07-13 00:49:59 -07:00
vfwmsac-vp.ll
[RISCV] Teach performCombineVMergeAndVOps to handle instructions FMA instructions.
2023-05-29 19:44:43 -07:00
vfwmsac.ll
[5/8][RISCV] Add rounding mode control variant for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac
2023-07-13 00:49:59 -07:00
vfwmul-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwmul.ll
[3/8][RISCV] Add rounding mode control variant for vfmul, vfdiv, vfrdiv, vfwmul
2023-07-13 00:43:54 -07:00
vfwnmacc-vp.ll
[RISCV] Update RISCVISD::VFWMADD_VLL isel patterns to allow a mask that isn't all ones.
2023-05-15 22:47:30 -07:00
vfwnmacc.ll
[5/8][RISCV] Add rounding mode control variant for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac
2023-07-13 00:49:59 -07:00
vfwnmsac-vp.ll
[RISCV] Update RISCVISD::VFWMADD_VLL isel patterns to allow a mask that isn't all ones.
2023-05-15 22:47:30 -07:00
vfwnmsac.ll
[5/8][RISCV] Add rounding mode control variant for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac
2023-07-13 00:49:59 -07:00
vfwredosum.ll
[8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
2023-07-13 00:55:10 -07:00
vfwredusum.ll
[8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
2023-07-13 00:55:10 -07:00
vfwsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwsub.ll
[2/8][RISCV] Add rounding mode control variant for vfwadd, vfwsub
2023-07-13 00:42:00 -07:00
vfwsub.w.ll
[2/8][RISCV] Add rounding mode control variant for vfwadd, vfwsub
2023-07-13 00:42:00 -07:00
vid.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
viota.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vitofp-constrained-sdnode.ll
[RISCV] Support vector type strict_[su]int_to_fp and strict_fp_to_[su]int.
2023-04-06 10:09:44 +08:00
vitofp-sdnode.ll
[RISCV] Improve 4x and 8x (s/u)int_to_fp.
2023-01-06 08:39:14 -08:00
vle_vid-vfcvt.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vle.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vleff-vlseg2ff-output.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
vleff.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vlm.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vloxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vloxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vloxseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vloxseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlse.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlsegff-rv32-dead.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlsegff-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlsegff-rv64-dead.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlsegff-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlsseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vlsseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vluxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vluxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vluxseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vluxseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vmacc-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
vmacc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmadc.carry.in.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmadc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmadd.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmand.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmandn.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmarith-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmax-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmax-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vmax.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmaxu-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vmaxu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
vmaxu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmclr.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmerge.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfeq.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfge.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfgt.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfle.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmflt.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfne.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmin-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmin-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vmin.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vminu-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vminu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
vminu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmnand.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmnor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmorn.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmsbc.borrow.in.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsbc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsbf.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmseq.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmset.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmsge.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsgeu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsgt.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsgtu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsif.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmsle.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsleu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmslt.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsltu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsne.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsof.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmul-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vmul-vp-mask.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vmul.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmulh-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmulh.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmulhsu.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmulhu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmulhu.ll
[RISCV] Refactor predicates for rvv intrinsic patterns.
2023-05-17 09:47:52 +08:00
vmv-copy.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vmv.s.x-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.s.x-rv64.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
vmv.v.v-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.v.v-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.v.x-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.v.x-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.x.s-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.x.s-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmxnor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmxor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnclip.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vnclipu.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vnmsac-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
vnmsac.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vnmsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnmsub.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vnsra-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsra-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsra-sdnode.ll
[DAG] Teach isConstOrConstSplat about SPLAT_VECTORs
2022-12-08 11:53:25 +00:00
vnsrl-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsrl-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsrl-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vor-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vor.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vpgather-sdnode.ll
[RISCV] Narrow types of index operand matched pattern (shl (zext), C).
2023-07-14 15:45:44 +08:00
vpload.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
vpmerge-sdnode.ll
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
vpscatter-sdnode.ll
[RISCV] Narrow types of index operand matched pattern (shl (zext), C).
2023-07-14 15:45:44 +08:00
vpstore.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
vredand.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vredmax.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vredmaxu.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vredmin.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vredminu.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vredor.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vredsum.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vreductions-fp-sdnode.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
vreductions-fp-vp.ll
[RISCV][RISCVISelLowering] Add tail agnostic policy operand to VECREDUCE instructions
2023-03-25 02:42:13 -07:00
vreductions-int-vp.ll
[RISCV][RISCVISelLowering] Add tail agnostic policy operand to VECREDUCE instructions
2023-03-25 02:42:13 -07:00
vreductions-int.ll
[RISCV][InsertVSETVLI] Split out demanded property for zero/non-zero of VL
2023-01-03 14:47:13 -08:00
vreductions-mask-vp.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
vreductions-mask.ll
[RISCV] Use zeroext instead of signext in mask reduction tests. NFC
2023-01-17 15:15:45 -08:00
vredxor.ll
[RISCV] Merge rv32/rv64 vector reduction intrinsic tests that have the same content. NFC.
2023-07-11 19:04:56 +08:00
vrem-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrem-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vrem.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vremu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vremu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vremu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vrgather-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgather-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgatherei16-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgatherei16-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgatherei16-subreg-liveness.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vrsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vrsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsadd-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsadd-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsaddu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsaddu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsaddu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsbc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vscale-power-of-two.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
vse.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vselect-fp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vselect-int.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vselect-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vselect-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vsetvl-ext.ll
[RISCV] Make vsetvli intrinsics default to MA.
2023-02-13 10:39:55 -08:00
vsetvli-insert-crossbb.ll
[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
2023-07-13 00:47:27 -07:00
vsetvli-insert-crossbb.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vsetvli-insert.ll
[2/8][RISCV] Add rounding mode control variant for vfwadd, vfwsub
2023-07-13 00:42:00 -07:00
vsetvli-insert.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vsetvli-intrinsics.ll
[RISCV] Treat __riscv_vsetvl_*(-1) as vlmax.
2023-06-16 09:23:01 -07:00
vsetvli-regression.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vsext.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vshl-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vshl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vsitofp-vp.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vslide1down-constant-vl-rv32.ll
[RISCV] Make vsetvli intrinsics default to MA.
2023-02-13 10:39:55 -08:00
vslide1down-rv32.ll
[RISCV] Make vsetvli intrinsics default to MA.
2023-02-13 10:39:55 -08:00
vslide1down-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslide1up-constant-vl-rv32.ll
[RISCV] Make vsetvli intrinsics default to MA.
2023-02-13 10:39:55 -08:00
vslide1up-rv32.ll
[RISCV] Make vsetvli intrinsics default to MA.
2023-02-13 10:39:55 -08:00
vslide1up-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslidedown-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslidedown-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslideup-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslideup-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsll.ll
[RISCV] Merge rv32/rv64 vector single-width shift intrinsic tests that have the same content. NFC.
2023-07-16 13:09:10 +08:00
vsm.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsmul-rv32.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vsmul-rv64.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vsoxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsoxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsoxseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vsoxseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vsplats-fp.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
vsplats-i1.ll
Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
2023-05-10 11:51:51 -07:00
vsplats-i64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsplats-zfa.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
vsra-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vsra-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsra.ll
[RISCV] Merge rv32/rv64 vector single-width shift intrinsic tests that have the same content. NFC.
2023-07-16 13:09:10 +08:00
vsrl-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vsrl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsrl.ll
[RISCV] Merge rv32/rv64 vector single-width shift intrinsic tests that have the same content. NFC.
2023-07-16 13:09:10 +08:00
vsse.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vsseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vssra-rv32.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssra-rv64.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssrl-rv32.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssrl-rv64.ll
[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu
2023-06-20 11:09:24 -07:00
vssseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vssseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vssub-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssub-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssubu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssubu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssubu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsub-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vsub-vp-mask.ll
[RISCV] Move some vector tests to rvv directory. NFC
2023-04-06 10:28:41 +01:00
vsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsuxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsuxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsuxseg-rv32.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vsuxseg-rv64.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vtrunc-vp-mask.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vtrunc-vp.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vtruncs-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vuitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vuitofp-vp.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
vwadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwadd-vp.ll
[RISCV] Add isel patterns to form tail undisturbed vwadd(u).wv from vwadd(u)_vl+vp_merge.
2023-01-09 16:44:11 -08:00
vwadd.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwadd.w.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwaddu.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwaddu.w.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwmacc-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmacc-vp.ll
[RISCV] Add some tail undisturbed vwmacc tests. NFC
2023-05-30 15:16:00 -07:00
vwmacc.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwmaccsu-vp.ll
[RISCV] Introduce RISCVISD::VWMACC(U/SU)_VL opcode
2023-06-16 16:11:35 -07:00
vwmaccsu.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwmaccu-vp.ll
[RISCV] Add some tail undisturbed vwmacc tests. NFC
2023-05-30 15:16:00 -07:00
vwmaccu.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwmaccus.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwmul-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmul.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwmulsu.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwmulu.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwredsum.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwredsumu.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsub.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwsub.w.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwsubu.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vwsubu.w.ll
[RISCV] Merge rv32/rv64 vector widening intrinsic tests that have the same content. NFC.
2023-07-11 16:25:12 +08:00
vxor-sdnode.ll
[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
2023-06-29 16:45:16 +08:00
vxor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vxor.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vxrm.mir
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
vzext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vzext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vzext.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
wrong-chain-fixed-load.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
wrong-stack-offset-for-rvv-object.mir
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
wrong-stack-slot-rv32.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
wrong-stack-slot-rv64.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
xsfvcp-x.ll
[RISCV] Support LLVM IR intrinsics for xsfvcp extension.
2023-04-24 03:10:13 -07:00
xsfvcp-xv.ll
[RISCV] Support LLVM IR intrinsics for xsfvcp extension.
2023-04-24 03:10:13 -07:00
xsfvcp-xvv.ll
[RISCV] Support LLVM IR intrinsics for xsfvcp extension.
2023-04-24 03:10:13 -07:00
xsfvcp-xvw.ll
[RISCV] Support LLVM IR intrinsics for xsfvcp extension.
2023-04-24 03:10:13 -07:00
xtheadvdot-vmaqa.ll
[RISCV] Add codegen support for RISCV XTHeadVdot Extension
2023-01-10 18:12:43 +08:00
xtheadvdot-vmaqasu.ll
[RISCV] Add codegen support for RISCV XTHeadVdot Extension
2023-01-10 18:12:43 +08:00
xtheadvdot-vmaqau.ll
[RISCV] Add codegen support for RISCV XTHeadVdot Extension
2023-01-10 18:12:43 +08:00
xtheadvdot-vmaqaus.ll
[RISCV] Add codegen support for RISCV XTHeadVdot Extension
2023-01-10 18:12:43 +08:00
zve32-types.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
zvlsseg-copy.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
zvlsseg-spill.mir
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
zvlsseg-zero-vl.ll
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00