d89d45ca9a
This changes the default value used for mask policy from mask undisturbed to mask agnostic. In hardware, there may be a minor preference for ta/ma, but since this is only going to apply to instructions which don't use the mask policy bit, this is functionally mostly a nop. The main value is to make future changes to using MA when legal for masked instructions easier to review by reducing test churn.
The prior code was motivated by a desire to minimize state transitions between masked and unmasked code. This patch achieves the same effect using the demanded field logic (landed in afb45ff), and there are no regressions I spotted in the test diffs. (Given the size, I have only been able to skim.) I do want to call out that regressions are possible here; the demanded analysis only works on a block local scope right now, so e.g. a tight loop mixing masked and unmasked computation might see an extra vsetvli or two.
Differential Revision: https://reviews.llvm.org/D133803
166 lines
5.5 KiB
LLVM
166 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv1f16_nxv1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 1 x half> %va to <vscale x 1 x float>
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ret <vscale x 1 x float> %evec
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}
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define <vscale x 1 x double> @vfpext_nxv1f16_nxv1f64(<vscale x 1 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv1f16_nxv1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v8, v9
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 1 x half> %va to <vscale x 1 x double>
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ret <vscale x 1 x double> %evec
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}
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define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32(<vscale x 2 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv2f16_nxv2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 2 x half> %va to <vscale x 2 x float>
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ret <vscale x 2 x float> %evec
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}
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define <vscale x 2 x double> @vfpext_nxv2f16_nxv2f64(<vscale x 2 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv2f16_nxv2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v8, v10
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 2 x half> %va to <vscale x 2 x double>
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ret <vscale x 2 x double> %evec
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}
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define <vscale x 4 x float> @vfpext_nxv4f16_nxv4f32(<vscale x 4 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv4f16_nxv4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v10, v8
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 4 x half> %va to <vscale x 4 x float>
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ret <vscale x 4 x float> %evec
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}
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define <vscale x 4 x double> @vfpext_nxv4f16_nxv4f64(<vscale x 4 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv4f16_nxv4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v12, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v8, v12
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 4 x half> %va to <vscale x 4 x double>
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ret <vscale x 4 x double> %evec
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}
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define <vscale x 8 x float> @vfpext_nxv8f16_nxv8f32(<vscale x 8 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv8f16_nxv8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v12, v8
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; CHECK-NEXT: vmv4r.v v8, v12
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 8 x half> %va to <vscale x 8 x float>
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ret <vscale x 8 x float> %evec
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}
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define <vscale x 8 x double> @vfpext_nxv8f16_nxv8f64(<vscale x 8 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv8f16_nxv8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v16, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v8, v16
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 8 x half> %va to <vscale x 8 x double>
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ret <vscale x 8 x double> %evec
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}
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define <vscale x 16 x float> @vfpext_nxv16f16_nxv16f32(<vscale x 16 x half> %va) {
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;
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; CHECK-LABEL: vfpext_nxv16f16_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v16, v8
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; CHECK-NEXT: vmv8r.v v8, v16
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 16 x half> %va to <vscale x 16 x float>
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ret <vscale x 16 x float> %evec
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}
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define <vscale x 1 x double> @vfpext_nxv1f32_nxv1f64(<vscale x 1 x float> %va) {
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;
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; CHECK-LABEL: vfpext_nxv1f32_nxv1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
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ret <vscale x 1 x double> %evec
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}
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define <vscale x 2 x double> @vfpext_nxv2f32_nxv2f64(<vscale x 2 x float> %va) {
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;
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; CHECK-LABEL: vfpext_nxv2f32_nxv2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v10, v8
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
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ret <vscale x 2 x double> %evec
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}
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define <vscale x 4 x double> @vfpext_nxv4f32_nxv4f64(<vscale x 4 x float> %va) {
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;
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; CHECK-LABEL: vfpext_nxv4f32_nxv4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v12, v8
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; CHECK-NEXT: vmv4r.v v8, v12
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
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ret <vscale x 4 x double> %evec
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}
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define <vscale x 8 x double> @vfpext_nxv8f32_nxv8f64(<vscale x 8 x float> %va) {
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;
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; CHECK-LABEL: vfpext_nxv8f32_nxv8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v16, v8
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; CHECK-NEXT: vmv8r.v v8, v16
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; CHECK-NEXT: ret
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%evec = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
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ret <vscale x 8 x double> %evec
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}
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