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clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel
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Nikita Popov eb86de63d9 [IR] Require that ptrmask mask matches pointer index size (#69343) 
Currently, we specify that the ptrmask intrinsic allows the mask to have
any size, which will be zero-extended or truncated to the pointer size.

However, what semantics of the specified GEP expansion actually imply is
that the mask is only meaningful up to the pointer type *index* size --
any higher bits of the pointer will always be preserved. In other words,
the mask gets 1-extended from the index size to the pointer size. This
is also the behavior we want for CHERI architectures.

This PR makes two changes:
* It spells out the interaction with the pointer type index size more
explicitly.
* It requires that the mask matches the pointer type index size. The
intention here is to make handling of this intrinsic more robust, to
avoid accidental mix-ups of pointer size and index size in code
generating this intrinsic. If a zero-extend or truncate of the mask is
desired, it should just be done explicitly in IR. This also cuts down on
the amount of testing we have to do, and things transforms needs to
check for.

As far as I can tell, we don't actually support pointers with different
index type size at the SDAG level, so I'm just asserting the sizes match
there for now. Out-of-tree targets using different index sizes may need
to adjust that code.
2023-10-24 09:54:29 +02:00
..
add_shl.ll
[GlobalISel] Implement commuting shl (add/or x, c1), c2 -> add/or (shl x, c2), c1 << c2
2023-05-08 22:37:43 -07:00
add.v2i16.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
add.vni16.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
addo.ll
…
amdgpu-irtranslator.ll
…
andn2.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
artifact-combiner-anyext.mir
…
artifact-combiner-asserts.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
artifact-combiner-build-vector.mir
…
artifact-combiner-concat-vectors.mir
…
artifact-combiner-cse-leaves-dead-cast.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
artifact-combiner-extract.mir
…
artifact-combiner-sext.mir
…
artifact-combiner-trunc.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
artifact-combiner-unmerge-values.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
artifact-combiner-zext.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
ashr.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
assert-align.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
atomic_load_local.ll
…
atomic_optimizations_mul_one.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
atomic_store_local.ll
…
atomicrmw_udec_wrap.ll
AMDGPU: Add syncscopes to some atomic tests
2023-08-08 14:38:06 -04:00
atomicrmw_uinc_wrap.ll
AMDGPU: Add syncscopes to some atomic tests
2023-08-08 14:38:06 -04:00
bool-legalization.ll
AMDGPU/GlobalISel: Widen s1 SGPR constants during regbankselect
2023-01-10 14:45:23 -05:00
br-constant-invalid-sgpr-copy.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
bswap.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-atomic-fadd.f32-rtn.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-atomic-fadd.f64.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-atomic-fadd.v2f16-rtn.ll
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
buffer-schedule.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
bug-legalization-artifact-combiner-dead-def.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
bug-legalization-artifact-combiner-dead-def.mir
…
call-outgoing-stack-args.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
clamp-fmed3-const-combine.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
clamp-minmax-const-combine.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-add-nullptr.mir
…
combine-add-to-ptradd.mir
…
combine-amdgpu-cvt-f32-ubyte.mir
[GlobalISel] Combine out-of-range shifts to undef.
2023-02-17 15:05:00 -08:00
combine-ashr-narrow.mir
[GlobalISel] Combine out-of-range shifts to undef.
2023-02-17 15:05:00 -08:00
combine-ext-legalizer.mir
…
combine-fabs-fneg.mir
…
combine-fcanonicalize.mir
AMDGPU: Fix broken denormal constant folding of canonicalize
2023-07-17 19:54:20 -04:00
combine-fma-add-ext-fma.ll
…
combine-fma-add-ext-mul.ll
…
combine-fma-add-fma-mul.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-fma-add-mul-post-legalize.mir
…
combine-fma-add-mul-pre-legalize.mir
[AMDGPU] Regen combine-fma-add-mul-pre-legalize.mir
2023-09-12 08:50:12 +02:00
combine-fma-add-mul.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-fma-sub-ext-mul.ll
…
combine-fma-sub-ext-neg-mul.ll
…
combine-fma-sub-mul.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-fma-sub-neg-mul.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
combine-fma-unmerge-values.mir
AMDGPU: Partially fix not respecting dynamic denormal mode
2023-07-11 15:14:52 -04:00
combine-fold-binop-into-select.mir
[GlobalISel] New combine to commute constant operands to the RHS
2023-01-05 11:12:40 +00:00
combine-foldable-fneg.mir
…
combine-fsh.mir
…
combine-fsub-fneg.mir
…
combine-itofp.mir
…
combine-lshr-narrow.mir
[GlobalISel] Combine out-of-range shifts to undef.
2023-02-17 15:05:00 -08:00
combine-or-redundant.mir
…
combine-redundant-and.mir
…
combine-redundant-neg.mir
…
combine-rot.mir
…
combine-rsq.ll
AMDGPU: Correctly lower llvm.sqrt.f32
2023-09-12 23:22:54 +03:00
combine-rsq.mir
AMDGPU: Fix more unsafe rsq formation
2023-08-23 19:28:49 -04:00
combine-sext-inreg.mir
…
combine-shift-imm-chain-illegal-types.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shift-imm-chain-shlsat.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
combine-shift-imm-chain.ll
…
combine-shift-of-shifted-logic-shlsat.mir
…
combine-shift-of-shifted-logic.ll
…
combine-shl-from-extend-narrow.postlegal.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shl-from-extend-narrow.prelegal.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shl-narrow.mir
[GlobalISel] Combine out-of-range shifts to undef.
2023-02-17 15:05:00 -08:00
combine-short-clamp.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
combine-trunc-shift.mir
…
combine-urem-pow-2.mir
…
combine-zext-trunc.mir
…
combiner-crash.ll
…
compute-num-sign-bits-med3.mir
AMDGPU: Implement known bits functions for min3/max3/med3
2023-06-10 10:58:44 -04:00
constant-bus-restriction.ll
…
crash-stack-address-O0.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
cvt_f32_ubyte.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
dereferenceable-declaration.ll
[GlobalISel] introduce MIFlag::NoConvergent
2023-08-20 21:14:46 +05:30
divergent-control-flow.ll
…
dropped_debug_info_assert.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
dummy-target.ll
[AMDGPU] Remove function with incompatible features
2023-02-21 10:42:39 +01:00
dynamic-alloca-divergent.ll
…
dynamic-alloca-uniform.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
extractelement-stack-lower.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
extractelement.i8.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
extractelement.i16.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
extractelement.i128.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
extractelement.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
fdiv.f16.ll
[GlobalISel] Fold fmul x, 1.0 -> x (#65379)
2023-09-06 03:14:16 +08:00
fdiv.f32.ll
[AMDGPU] Correctly restore FP mode in FDIV32 lowering (#66346)
2023-09-15 08:11:01 +02:00
fdiv.f64.ll
[GlobalISel] Fold fmul x, 1.0 -> x (#65379)
2023-09-06 03:14:16 +08:00
flat-atomic-fadd.f32.ll
…
flat-atomic-fadd.f64.ll
…
flat-atomic-fadd.v2f16.ll
…
flat-scratch-init.gfx.ll
…
flat-scratch-init.ll
…
flat-scratch.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
floor.f64.ll
[AMDGPU] Remove unused check lines from GlobalISel IR tests
2023-04-19 15:13:02 +01:00
fma.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
fmax_legacy.ll
…
fmed3-min-max-const-combine.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
fmin_legacy.ll
…
fmul.v2f16.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
fp64-atomics-gfx90a.ll
[AMDGPU] Add DAG ISel support for preloaded kernel arguments
2023-09-25 09:32:59 -07:00
fp-atomics-gfx940.ll
[AMDGPU] Do not exapnd fp atomics on gfx940
2023-02-08 13:22:04 -08:00
fpow.ll
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
frem.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
fshl.ll
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
fshr.ll
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
function-returns.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
function-returns.v2i65.ll
…
global-atomic-fadd.f32-no-rtn.ll
[AMDGPU] Reorder atomic optimizer to avoid CAS loop.
2023-08-30 12:05:21 -04:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU] Reorder atomic optimizer to avoid CAS loop.
2023-08-30 12:05:21 -04:00
global-atomic-fadd.f64.ll
…
global-atomic-fadd.v2f16-no-rtn.ll
…
global-atomic-fadd.v2f16-rtn.ll
…
global-value.illegal.ll
…
global-value.ll
[AMDGPU] Use absolute relocations when compiling for AMDPAL and Mesa3D (#67791)
2023-10-10 09:22:02 +02:00
hip.extern.shared.array.ll
…
i1-copy.ll
…
image-waterfall-loop-O0.ll
[AMDGPU] Introduce AMDGPU::SGPR_SPILL asm comment flag (#67091)
2023-09-29 11:15:01 +05:30
implicit-kernarg-backend-usage-global-isel.ll
Revert "[AMDGPU] Remove Code Object V3 (#67118)"
2023-10-18 12:55:36 +02:00
inline-asm-mismatched-size.ll
…
inline-asm.ll
…
insertelement-stack-lower.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
insertelement.i8.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
insertelement.i16.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
insertelement.large.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
insertelement.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
inst-select-abs.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-add.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-add.s16.mir
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
inst-select-amdgcn.class.mir
…
inst-select-amdgcn.class.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.cos.mir
…
inst-select-amdgcn.cos.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.cvt.pk.i16.mir
…
inst-select-amdgcn.cvt.pk.u16.mir
…
inst-select-amdgcn.cvt.pknorm.i16.mir
…
inst-select-amdgcn.cvt.pknorm.u16.mir
…
inst-select-amdgcn.cvt.pkrtz.mir
…
inst-select-amdgcn.ds.swizzle.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.exp.compr.mir
…
inst-select-amdgcn.exp.mir
…
inst-select-amdgcn.fcmp.constants.w32.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.fcmp.constants.w64.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.fmad.ftz.mir
…
inst-select-amdgcn.fmed3.mir
…
inst-select-amdgcn.fmed3.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.fract.mir
…
inst-select-amdgcn.fract.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.groupstaticsize.mir
…
inst-select-amdgcn.mbcnt.lo.mir
…
inst-select-amdgcn.mul.u24.mir
…
inst-select-amdgcn.mulhi.i24.mir
…
inst-select-amdgcn.mulhi.u24.mir
…
inst-select-amdgcn.rcp.legacy.mir
…
inst-select-amdgcn.rcp.mir
…
inst-select-amdgcn.rcp.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.readfirstlane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.reloc.constant.mir
…
inst-select-amdgcn.rsq.clamp.mir
…
inst-select-amdgcn.rsq.legacy.mir
…
inst-select-amdgcn.rsq.mir
…
inst-select-amdgcn.rsq.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgcn.s.barrier.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
inst-select-amdgcn.s.sendmsg.mir
…
inst-select-amdgcn.sffbh.mir
…
inst-select-amdgcn.sin.mir
…
inst-select-amdgcn.sin.s16.mir
[AMDGPU] Regenerate some GlobalISel checks
2023-06-05 11:21:31 +01:00
inst-select-amdgpu-atomic-cmpxchg-flat.mir
[AMDGPU] Run update scripts on existing tests. NFC
2023-02-27 09:48:57 +01:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-amdgpu-ffbh-u32.mir
…
inst-select-amdgpu-ffbl-b32.mir
…
inst-select-amdgpu-wave-address.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-and.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-anyext.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-ashr.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-ashr.s16.mir
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
inst-select-ashr.v2s16.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
inst-select-atomic-cmpxchg-local.mir
…
inst-select-atomic-cmpxchg-region.mir
…
inst-select-atomicrmw-add-flat.mir
AMDGPU: Update checks for a couple of tests. NFC
2023-03-09 15:09:19 +01:00
inst-select-atomicrmw-add-global.mir
AMDGPU: Update checks for a couple of tests. NFC
2023-03-09 15:09:19 +01:00
inst-select-atomicrmw-fadd-local.mir
…
inst-select-atomicrmw-fadd-region.mir
…
inst-select-atomicrmw-xchg-local.mir
…
inst-select-atomicrmw-xchg-region.mir
…
inst-select-bitcast.mir
…
inst-select-bitreverse.mir
…
inst-select-br.mir
…
inst-select-brcond.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-bswap.mir
…
inst-select-build-vector-trunc.v2s16.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-build-vector.mir
…
inst-select-concat-vectors.mir
…
inst-select-constant.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-copy.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-ctlz-zero-undef.mir
…
inst-select-ctpop.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-cttz-zero-undef.mir
…
inst-select-extract-vector-elt.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-extract.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-fabs.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-fadd.s16.mir
…
inst-select-fadd.s32.mir
…
inst-select-fadd.s64.mir
…
inst-select-fcanonicalize.mir
[AMDGPU] Switch to using real True16 operands.
2023-09-25 18:21:13 +01:00
inst-select-fceil.mir
…
inst-select-fceil.s16.mir
…
inst-select-fcmp.mir
…
inst-select-fcmp.s16.mir
…
inst-select-fconstant.mir
…
inst-select-fexp2.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
inst-select-ffloor.s16.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
inst-select-ffloor.s32.mir
…
inst-select-ffloor.s64.mir
…
inst-select-fma.s32.mir
…
inst-select-fmad.s32.mir
…
inst-select-fmaxnum-ieee.mir
…
inst-select-fmaxnum-ieee.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fmaxnum-ieee.v2s16.mir
…
inst-select-fmaxnum.mir
…
inst-select-fmaxnum.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fmaxnum.v2s16.mir
…
inst-select-fminnum-ieee.mir
…
inst-select-fminnum-ieee.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fminnum-ieee.v2s16.mir
…
inst-select-fminnum.mir
…
inst-select-fminnum.s16.mir
Reapply "[AMDGPU] Introduce real and keep fake True16 instructions."
2023-09-23 22:07:41 +01:00
inst-select-fminnum.v2s16.mir
…
inst-select-fmul.mir
AMDGPU: Select f64 fmul by negative power of 2 to ldexp
2023-08-23 20:36:01 -04:00
inst-select-fmul.v2s16.mir
…
inst-select-fneg.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-fptosi.mir
…
inst-select-fptoui.mir
…
inst-select-fract.f64.mir
AMDGPU/GlobalISel: Fix broken test
2023-05-18 21:20:06 +01:00
inst-select-frame-index.mir
…
inst-select-freeze.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
inst-select-frint.mir
…
inst-select-frint.s16.mir
…
inst-select-fshr.mir
…
inst-select-i1-copy.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-icmp.mir
…
inst-select-icmp.s16.mir
…
inst-select-icmp.s64.mir
…
inst-select-implicit-def.mir
…
inst-select-insert-vector-elt.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-insert.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-intrinsic-trunc.mir
…
inst-select-intrinsic-trunc.s16.mir
…
inst-select-inttoptr.mir
…
inst-select-load-atomic-flat.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-load-atomic-global.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-load-atomic-local.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-load-constant.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-load-flat.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-load-global-saddr.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-load-global.mir
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
inst-select-load-global.s96.mir
…
inst-select-load-local-128.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-load-local.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-load-private.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
inst-select-load-smrd.mir
[AMDGPU] Don't select _SGPR forms of SMEM instructions on GFX9+
2023-04-17 16:23:30 +01:00
inst-select-lshr.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-lshr.s16.mir
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
inst-select-lshr.v2s16.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
inst-select-mad_64_32.mir
…
inst-select-merge-values.mir
…
inst-select-mul.mir
…
inst-select-or.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-add3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-and-or.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-or3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-smed3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-smed3.s16.mir
…
inst-select-pattern-umed3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-umed3.s16.mir
…
inst-select-pattern-xor3.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-phi.mir
…
inst-select-ptr-add.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-ptrmask.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-ptrtoint.mir
…
inst-select-returnaddress.mir
…
inst-select-sbfx.mir
…
inst-select-scalar-float-sop1.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
inst-select-scalar-float-sop2.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
inst-select-scalar-float-sopc.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
inst-select-scalar-packed.xfail.mir
…
inst-select-select.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-sext-inreg.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-sext.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-sextload-local.mir
…
inst-select-shl.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-shl.s16.mir
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
inst-select-shl.v2s16.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
inst-select-sitofp.mir
…
inst-select-smax.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-smin.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-smulh.mir
…
inst-select-stacksave-stackrestore.invalid.mir
AMDGPU/GlobalISel: Handle stacksave/stackrestore
2023-08-11 10:25:01 -04:00
inst-select-stacksave-stackrestore.mir
AMDGPU/GlobalISel: Handle stacksave/stackrestore
2023-08-11 10:25:01 -04:00
inst-select-store-atomic-flat.mir
…
inst-select-store-atomic-local.mir
…
inst-select-store-flat.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-store-global.mir
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
inst-select-store-global.s96.mir
…
inst-select-store-local.mir
[AMDGPU] Autogenerate checks for several tests. NFCI
2023-02-16 10:54:34 +01:00
inst-select-store-private.mir
AMDGPU/GlobalISel: Use SGPR results for G_AMDGPU_WAVE_ADDRESS
2023-07-31 19:16:11 -04:00
inst-select-sub.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-trunc.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-trunc.v2s16.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-uadde.gfx10.mir
…
inst-select-uadde.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-uaddo.mir
…
inst-select-ubfx.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
inst-select-uitofp.mir
…
inst-select-umax.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-umin.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-umulh.mir
…
inst-select-unmerge-values.mir
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
inst-select-usube.gfx10.mir
…
inst-select-usube.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-usubo.mir
…
inst-select-xor.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-zext.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-zextload-local.mir
…
irtranslator-amdgcn-sendmsg.ll
…
irtranslator-amdgpu_kernel-system-sgprs.ll
AMDGPU: Don't run AMDGPUAttributor with -O0
2023-06-08 07:52:37 -04:00
irtranslator-amdgpu_kernel.ll
AMDGPU: Don't run AMDGPUAttributor with -O0
2023-06-08 07:52:37 -04:00
irtranslator-amdgpu_ps.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-amdgpu_vs.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-assert-align.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
irtranslator-atomicrmw.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
irtranslator-call-abi-attribute-hints.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
irtranslator-call-implicit-args.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
irtranslator-call-non-fixed.ll
[GlobalISel] introduce MIFlag::NoConvergent
2023-08-20 21:14:46 +05:30
irtranslator-call-return-values.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
irtranslator-call-sret.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
irtranslator-call.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
irtranslator-constant-fold-vector-op.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
irtranslator-constantexpr.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
irtranslator-constrained-fp.ll
…
irtranslator-fast-math-flags.ll
…
irtranslator-fence.ll
…
irtranslator-fixed-function-abi-vgpr-args.ll
…
irtranslator-function-args.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-function-args.v2i65.ll
…
irtranslator-getelementptr.ll
…
irtranslator-indirect-call.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
irtranslator-inline-asm.ll
[AMDGPU] Add True16 register classes.
2023-09-22 10:17:02 +01:00
irtranslator-invariant.ll
…
irtranslator-memory-intrinsics.ll
…
irtranslator-metadata.ll
…
irtranslator-non-integral-address-spaces-vectors.ll
Add 'REQUIRES: asserts' to test added in D150002 (53a4adc) because it tests for a crash that is caused by an assertion failure.
2023-05-12 19:01:52 -07:00
irtranslator-non-integral-address-spaces.ll
[GlobalISel] Handle ptr size != index size in IRTranslator, CodeGenPrepare
2023-05-12 16:21:01 +00:00
irtranslator-ptrmask.ll
[IR] Require that ptrmask mask matches pointer index size (#69343)
2023-10-24 09:54:29 +02:00
irtranslator-readnone-intrinsic-callsite.ll
…
irtranslator-sat.ll
…
irtranslator-sibling-call.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
irtranslator-struct-return-intrinsics.ll
…
irtranslator-tail-call.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
irtranslator-zext-vec-index.ll
…
lds-global-value.ll
…
lds-misaligned-bug.ll
…
lds-relocs.ll
…
lds-zero-initializer.ll
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
legalize-abs.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-add.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-addrspacecast.mir
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
legalize-amdgcn.if-invalid.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-amdgcn.if.xfail.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
…
legalize-and.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-anyext.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ashr.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-atomic-cmpxchg-with-success.mir
…
legalize-atomic-cmpxchg.mir
…
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd-global.mir
…
legalize-atomicrmw-fadd-local.mir
…
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
…
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
…
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-bitreverse.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-block-addr.mir
[CodeGen] Convert some tests to opaque pointers (NFC)
2023-01-05 13:21:20 +01:00
legalize-brcond.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-bswap.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-build-vector-splat.mir
[GlobalISel] Add G_BUILD_VECTOR[_TRUNC] to CSE
2023-01-05 10:15:31 +01:00
legalize-build-vector-trunc.mir
…
legalize-build-vector.mir
…
legalize-build-vector.s16.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
…
legalize-ctlz-zero-undef.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ctlz.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ctpop.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-cttz-zero-undef.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
legalize-cttz.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-extract-vector-elt.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
legalize-extract.mir
…
legalize-extractelement-crash.mir
…
legalize-fabs.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fadd.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fcanonicalize.mir
…
legalize-fceil.mir
…
legalize-fcmp-s32.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
legalize-fcmp.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
legalize-fconstant.mir
…
legalize-fcopysign.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fcos.mir
…
legalize-fdiv.mir
AMDGPU: Always use v_rcp_f16 and v_rsq_f16
2023-07-05 16:53:01 -04:00
legalize-fexp2.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fexp.mir
AMDGPU: Correctly lower llvm.exp.f32
2023-07-05 17:23:49 -04:00
legalize-ffloor.mir
…
legalize-flog2.mir
AMDGPU: Use correct lowering for llvm.log2.f32
2023-06-23 08:37:37 -04:00
legalize-flog10.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-flog.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-fma.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fmad.s16.mir
…
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fminnum.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fmul.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fneg.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fpext.mir
…
legalize-fpow.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fpowi.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fptosi.mir
…
legalize-fptoui.mir
…
legalize-fptrunc.mir
…
legalize-freeze.mir
…
legalize-frint.mir
…
legalize-fshl.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fshr.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-fsin.mir
…
legalize-fsqrt.mir
AMDGPU: Correctly lower llvm.sqrt.f32
2023-09-12 23:22:54 +03:00
legalize-fsub.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-icmp.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-implicit-def-s1025.mir
…
legalize-implicit-def.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-insert-vector-elt.mir
…
legalize-insert.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
AMDGPU: Use hex floats instead of ugly bitcasting
2023-07-17 19:54:04 -04:00
legalize-intrinsic-round.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-intrinsic-trunc.mir
…
legalize-inttoptr.mir
…
legalize-jump-table.mir
…
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU][True16] Fix ISel for A16 Image Instructions
2023-08-11 11:12:16 -04:00
legalize-llvm.amdgcn.image.dim.a16.ll
[AMDGPU][True16] Fix ISel for A16 Image Instructions
2023-08-11 11:12:16 -04:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-llvm.amdgcn.image.load.2d.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
Re-land "[AMDGPU] Define data layout entries for buffers""
2023-05-03 19:43:56 +00:00
legalize-llvm.amdgcn.image.load.3d.ll
Re-land "[AMDGPU] Define data layout entries for buffers""
2023-05-03 19:43:56 +00:00
legalize-llvm.amdgcn.image.sample.a16.ll
[AMDGPU][True16] Fix ISel for A16 Image Instructions
2023-08-11 11:12:16 -04:00
legalize-llvm.amdgcn.image.sample.d.ll
Re-land "[AMDGPU] Define data layout entries for buffers""
2023-05-03 19:43:56 +00:00
legalize-llvm.amdgcn.image.sample.g16.a16.ll
Re-land "[AMDGPU] Define data layout entries for buffers""
2023-05-03 19:43:56 +00:00
legalize-llvm.amdgcn.image.sample.g16.ll
Re-land "[AMDGPU] Define data layout entries for buffers""
2023-05-03 19:43:56 +00:00
legalize-llvm.amdgcn.image.store.2d.d16.ll
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-llvm.amdgcn.s.buffer.load.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-load-constant-32bit.mir
…
legalize-load-constant.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-load-flat.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-load-global.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-load-local.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-load-memory-metadata.mir
[CodeGen] Convert some tests to opaque pointers (NFC)
2023-01-05 13:21:20 +01:00
legalize-load-private.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-lshr.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-memcpy.mir
…
legalize-memcpyinline.mir
…
legalize-memmove.mir
…
legalize-memset.mir
…
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-mul.mir
…
legalize-or.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-phi.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ptr-add.mir
…
legalize-ptrmask.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ptrtoint.mir
…
legalize-rotl-rotr.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-sadde.mir
GlobalISel: Enable CSE for G_SEXT_INREG
2023-01-15 11:38:30 -05:00
legalize-saddo.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-saddsat.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-sbfx.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
legalize-sdiv.mir
…
legalize-select.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-sext-inreg.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-sext.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-sextload-constant-32bit.mir
…
legalize-sextload-flat.mir
…
legalize-sextload-global.mir
…
legalize-sextload-local.mir
…
legalize-sextload-private.mir
…
legalize-shl.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-shuffle-vector.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-shuffle-vector.s16.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-sitofp.mir
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
legalize-smax.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-smin.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-smulh.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-smulo.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-srem.mir
…
legalize-sshlsat.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ssube.mir
GlobalISel: Enable CSE for G_SEXT_INREG
2023-01-15 11:38:30 -05:00
legalize-ssubo.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ssubsat.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-store-global.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-store.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-strict_fsub.mir
…
legalize-sub.mir
…
legalize-trap.mir
AMDGPU: Avoid endpgm in middle of block for fallback trap lowering.
2023-06-09 21:04:38 -04:00
legalize-trunc.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-uadde.mir
…
legalize-uaddo.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-uaddsat.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ubfx.mir
…
legalize-udiv.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-uitofp.mir
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
legalize-umax.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-umin.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-umulh.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-umulo.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-unmerge-values.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-urem.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-ushlsat.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-usube.mir
…
legalize-usubo.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-usubsat.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-vector-args-gfx7.mir
…
legalize-vector-args-gfx8-plus.mir
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-xor.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-zext.mir
Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
2023-09-29 03:35:40 +02:00
legalize-zextload-constant-32bit.mir
…
legalize-zextload-flat.mir
…
legalize-zextload-global.mir
…
legalize-zextload-local.mir
…
legalize-zextload-private.mir
…
llvm.abs.ll
[AMDGPU][GlobalISel] Update applyMappingImpl for G_ABS and type v2s16
2023-08-02 12:27:06 +02:00
llvm.amdgcn.ballot.i32.ll
…
llvm.amdgcn.ballot.i64.ll
…
llvm.amdgcn.dispatch.id.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.div.fmas.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
llvm.amdgcn.div.scale.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
llvm.amdgcn.ds.fadd.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.ds.fmax.ll
…
llvm.amdgcn.ds.fmin.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.end.cf.i32.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.end.cf.i64.ll
…
llvm.amdgcn.fdot2.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.fmul.legacy.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.global.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.global.atomic.fadd.ll
…
llvm.amdgcn.if.break.i32.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.if.break.i64.ll
…
llvm.amdgcn.image.atomic.dim.a16.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] Reimplement the GFX11 early release VGPRs optimization
2023-06-19 17:12:54 +01:00
llvm.amdgcn.image.atomic.dim.mir
Re-land "[AMDGPU] Define data layout entries for buffers""
2023-05-03 19:43:56 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
llvm.amdgcn.image.gather4.dim.ll
…
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU] Don't assert that image intrinsics are supported
2023-04-16 19:54:55 +01:00
llvm.amdgcn.image.getresinfo.a16.ll
…
llvm.amdgcn.image.getresinfo.ll
…
llvm.amdgcn.image.load.1d.d16.ll
…
llvm.amdgcn.image.load.1d.ll
…
llvm.amdgcn.image.load.2d.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.image.load.3d.a16.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.image.load.3d.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.image.sample.cd.g16.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
llvm.amdgcn.image.sample.g16.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] Remove unused check lines from tests
2023-04-19 16:15:14 +01:00
llvm.amdgcn.image.store.2d.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.implicit.ptr.buffer.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Add tests on v_interp_p*_f16 with immediate parameters.
2023-03-30 13:48:43 +01:00
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
llvm.amdgcn.is.private.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
llvm.amdgcn.is.shared.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
llvm.amdgcn.kernarg.segment.ptr.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.make.buffer.rsrc.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.mfma.gfx90a.ll
…
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.queue.ptr.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.raw.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.tbuffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.s.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.sbfe.ll
[GlobalISel] New combine to commute constant operands to the RHS
2023-01-05 11:12:40 +00:00
llvm.amdgcn.sdot2.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.sdot4.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.sdot8.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.set.inactive.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.struct.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.sudot4.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.sudot8.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.trig.preop.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.ubfe.ll
…
llvm.amdgcn.udot2.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.udot4.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.udot8.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.update.dpp.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.wmma_32.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.wmma_64.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.workgroup.id.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.workitem.id.ll
[AMDGPU] Remove Code Object V2 (#65715)
2023-09-21 12:00:45 +02:00
llvm.amdgcn.wqm.demote.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
…
llvm.memcpy.inline.ll
CodeGen: Expand memory intrinsics in PreISelIntrinsicLowering
2023-06-09 21:04:37 -04:00
llvm.memcpy.ll
CodeGen: Expand memory intrinsics in PreISelIntrinsicLowering
2023-06-09 21:04:37 -04:00
llvm.memmove.ll
Recommit "[LSR] Consider post-inc form when creating extends/truncates."
2023-06-19 17:57:06 +01:00
llvm.memset.ll
CodeGen: Expand memory intrinsics in PreISelIntrinsicLowering
2023-06-09 21:04:37 -04:00
llvm.powi.ll
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
load-constant32bit.ll
…
load-constant.96.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
load-local.96.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
load-local.128.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
load-unaligned.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
localizer-wrong-insert-point.mir
…
localizer.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
lshr.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
memory-legalizer-atomic-fence.ll
…
merge-buffer-stores.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
minmaxabs.ll
…
mubuf-global.ll
AMDGPU: Add syncscopes to some atomic tests
2023-08-08 14:38:06 -04:00
mul-known-bits.i64.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
mul-known-bits.i64.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
mul.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
mul.v2i16.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
no-cse-nonlocal-convergent-instrs.mir
[CodeGen] Convert some tests to opaque pointers (NFC)
2023-01-05 13:21:20 +01:00
no-legalize-atomic.mir
…
non-entry-alloca.ll
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#66060)
2023-09-12 15:13:59 +05:30
orn2.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
postlegalizer-combiner-buildvector-identities.mir
…
postlegalizer-combiner-divrem.mir
…
postlegalizer-combiner-fcanonicalize.mir
…
postlegalizer-combiner-freeze.mir
…
postlegalizer-combiner-reassoc.mir
[GlobalISel] Fix infinite loop in reassociation combine
2023-07-16 14:15:24 +01:00
postlegalizer-combiner-sextload-from-sextinreg.mir
…
postlegalizer-combiner-trunc-bitcast-buildvector.mir
[GlobalISel] New combine to commute constant operands to the RHS
2023-01-05 11:12:40 +00:00
postlegalizer-combiner-unmerge-undef.mir
…
postlegalizer-combiner-zextload-from-and.mir
…
postlegalizercombiner-and.mir
…
postlegalizercombiner-ashr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-load-and-mask.mir
…
postlegalizercombiner-lshr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-sbfx.mir
…
postlegalizercombiner-select.mir
…
postlegalizercombiner-shl.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-ubfx.mir
…
prelegalizer-combiner-divrem.mir
…
prelegalizer-combiner-fptrunc_fpext.mir
GlobalISel: Fold out G_FPTRUNC(G_FPEXT)
2023-05-10 08:01:27 +01:00
prelegalizer-combiner-redundant-bitcast.mir
…
prelegalizer-combiner-sext_inreg-to-and.mir
…
regbankcombiner-clamp-fmed3-const.mir
AMDGPU/GlobalISel: Update test
2023-05-23 09:13:53 +01:00
regbankcombiner-clamp-minmax-const.mir
…
regbankcombiner-fmed3-minmax-const.mir
…
regbankcombiner-smed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankcombiner-umed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-abs.mir
[AMDGPU][GlobalISel] Update applyMappingImpl for G_ABS and type v2s16
2023-08-02 12:27:06 +02:00
regbankselect-add.s16.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-add.s32.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-add.v2s16.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn-exp-compr.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn-exp.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn-s-buffer-load.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ballot.i64.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.class.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.cvt.pkrtz.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.div.fmas.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.div.scale.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.ds.append.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.bpermute.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.consume.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.gws.init.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.gws.sema.v.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.ordered.add.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.ds.ordered.swap.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.ds.permute.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ds.swizzle.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.else.32.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.else.64.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.fcmp.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.fmul.legacy.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.groupstaticsize.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.icmp.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.image.load.1d.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.image.sample.1d.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.interp.mov.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.interp.p1.f16.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.interp.p1.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.interp.p2.f16.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.interp.p2.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.kernarg.segment.ptr.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.kill.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.lds.direct.load.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.lds.param.load.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.live.mask.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.mfma.gfx90a.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.mfma.gfx940.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.mfma.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.ps.live.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.raw.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.raw.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.readfirstlane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.readlane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.s.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.s.buffer.load.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.s.getpc.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.s.getreg.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.s.memrealtime.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.s.memtime.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.s.sendmsg.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.s.sendmsghalt.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.struct.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.buffer.store.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.update.dpp.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.wqm.demote.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.wqm.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgcn.wqm.vote.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.writelane.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.wwm.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgpu-ffbh-u32.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgpu-ffbl-b32.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-amdgpu-wave-address.mir
AMDGPU/GlobalISel: Use SGPR results for G_AMDGPU_WAVE_ADDRESS
2023-07-31 19:16:11 -04:00
regbankselect-and-s1.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-and.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-anyext.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ashr.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-assert-align.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-assert-zext.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomic-cmpxchg.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-add.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-and.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-fadd.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-max.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-min.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-or.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-sub.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-umax.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-umin.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-xchg.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-atomicrmw-xor.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-bitcast.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-bitreverse.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-block-addr.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-brcond.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-bswap.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-build-vector.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-concat-vector.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-constant.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-copy.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ctlz-zero-undef.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ctpop.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-cttz-zero-undef.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-default.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-dyn-stackalloc.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-extract-vector-elt.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-extract.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fabs.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fadd.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fcanonicalize.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fceil.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fcmp.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
regbankselect-fexp2.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-flog2.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fma.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fmul.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fneg.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fpext.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fptosi.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fptoui.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fptrunc.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-frame-index.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-freeze.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
regbankselect-frint.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fshr.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fsqrt.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-fsub.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-icmp.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-icmp.s16.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-illegal-copy.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-implicit-def.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-insert-vector-elt.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-insert.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-intrinsic-trunc.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-inttoptr.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-load.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-lshr.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-mad_64_32.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-merge-values.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-mul.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-or.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-phi-s1.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-phi.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ptr-add.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ptrmask.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ptrtoint.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-reg-sequence.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-sadde.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-salu-float.mir
[AMDGPU] Select gfx1150 SALU Float instructions (#66885)
2023-09-21 12:22:55 +02:00
regbankselect-sbfx.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-select.mir
[AMDGPU] Remove unused check lines from GlobalISel MIR tests
2023-04-19 15:03:32 +01:00
regbankselect-sext-inreg.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-sext.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-sextload.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-shl.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-sitofp.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-smax.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-smin.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-smulh.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-split-scalar-load-metadata.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ssube.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-sub.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-trunc.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-uadde.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-uaddo.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-ubfx.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-uitofp.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-umax.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-umin.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-umulh.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-uniform-load-noclobber.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-unmerge-values.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-usube.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-usubo.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-waterfall-agpr.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-widen-scalar-loads.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-xor.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-zext.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect-zextload.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
regbankselect.mir
AMDGPU/GlobalISel: Add stub custom regbankselect pass
2023-01-30 16:18:20 -04:00
saddsat.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
sbfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
sdiv.i32.ll
GlobalISel: Add shifts to constant_fold combine
2023-08-24 08:09:57 -04:00
sdiv.i64.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
sdivrem.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
select-to-fmin-fmax.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
sext_inreg.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
shader-epilogs.ll
…
shl-ext-reduce.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
shl.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
shlN_add.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
smed3.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
smrd.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
srem.i32.ll
GlobalISel: Add shifts to constant_fold combine
2023-08-24 08:09:57 -04:00
srem.i64.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
ssubsat.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
store-local.96.ll
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
store-local.128.ll
[GlobalISelEmitter] handle operand without MVT/class
2023-04-19 07:00:57 +00:00
strict_fma.f16.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f32.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f64.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
sub.v2i16.ll
AMDGPU/GlobalISel: Add test for packed sub selection
2023-10-05 10:07:57 -07:00
subo.ll
…
trunc.ll
…
uaddsat.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
ubfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
udiv.i32.ll
[GlobalISel] New combine to commute constant operands to the RHS
2023-01-05 11:12:40 +00:00
udiv.i64.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
udivrem.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
umed3.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
unsupported-load.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
unsupported-ptr-add.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
urem.i32.ll
[GlobalISel] New combine to commute constant operands to the RHS
2023-01-05 11:12:40 +00:00
urem.i64.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
usubsat.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
v_bfe_i32.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
widen-i8-i16-scalar-loads.ll
…
xnor.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
zextload.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00