12092a9691
Summary: This is a NFC change that removes the NFA->DFA construction and emission logic from DFAPacketizerEmitter and instead uses the generic DFAEmitter logic. This allows DFAPacketizer to use the Automaton class from Support and remove a bunch of logic there too. After this patch, DFAPacketizer is mostly logic for grepping Itineraries and collecting functional units, with no state machine logic. This will allow us to modernize by removing the 16-functional-unit limit and supporting non-itinerary functional units. This is all for followup patches. Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68992 llvm-svn: 375086
556 lines
19 KiB
C++
556 lines
19 KiB
C++
//===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class parses the Schedule.td file and produces an API that can be used
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// to reason about whether an instruction can be added to a packet on a VLIW
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// architecture. The class internally generates a deterministic finite
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// automaton (DFA) that models all possible mappings of machine instructions
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// to functional units as instructions are added to a packet.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "dfa-emitter"
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#include "CodeGenTarget.h"
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#include "DFAEmitter.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <set>
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#include <string>
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#include <unordered_map>
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#include <vector>
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using namespace llvm;
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// --------------------------------------------------------------------
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// Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp
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// DFA_MAX_RESTERMS * DFA_MAX_RESOURCES must fit within sizeof DFAInput.
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// This is verified in DFAPacketizer.cpp:DFAPacketizer::DFAPacketizer.
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//
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// e.g. terms x resource bit combinations that fit in uint32_t:
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// 4 terms x 8 bits = 32 bits
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// 3 terms x 10 bits = 30 bits
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// 2 terms x 16 bits = 32 bits
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//
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// e.g. terms x resource bit combinations that fit in uint64_t:
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// 8 terms x 8 bits = 64 bits
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// 7 terms x 9 bits = 63 bits
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// 6 terms x 10 bits = 60 bits
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// 5 terms x 12 bits = 60 bits
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// 4 terms x 16 bits = 64 bits <--- current
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// 3 terms x 21 bits = 63 bits
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// 2 terms x 32 bits = 64 bits
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//
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#define DFA_MAX_RESTERMS 4 // The max # of AND'ed resource terms.
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#define DFA_MAX_RESOURCES 16 // The max # of resource bits in one term.
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typedef uint64_t DFAInput;
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typedef int64_t DFAStateInput;
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#define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable.
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namespace {
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DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
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return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
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}
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/// Return the DFAInput for an instruction class input vector.
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/// This function is used in both DFAPacketizer.cpp and in
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/// DFAPacketizerEmitter.cpp.
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DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
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DFAInput InsnInput = 0;
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assert((InsnClass.size() <= DFA_MAX_RESTERMS) &&
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"Exceeded maximum number of DFA terms");
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for (auto U : InsnClass)
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InsnInput = addDFAFuncUnits(InsnInput, U);
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return InsnInput;
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}
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} // end anonymous namespace
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// --------------------------------------------------------------------
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#ifndef NDEBUG
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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//
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// dbgsInsnClass - When debugging, print instruction class stages.
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//
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void dbgsInsnClass(const std::vector<unsigned> &InsnClass);
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//
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// dbgsStateInfo - When debugging, print the set of state info.
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//
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void dbgsStateInfo(const std::set<unsigned> &stateInfo);
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//
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// dbgsIndent - When debugging, indent by the specified amount.
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//
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void dbgsIndent(unsigned indent);
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#endif
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//
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// class DFAPacketizerEmitter: class that generates and prints out the DFA
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// for resource tracking.
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//
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namespace {
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class DFAPacketizerEmitter {
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private:
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std::string TargetName;
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//
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// allInsnClasses is the set of all possible resources consumed by an
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// InstrStage.
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//
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std::vector<std::vector<unsigned>> allInsnClasses;
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RecordKeeper &Records;
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public:
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DFAPacketizerEmitter(RecordKeeper &R);
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//
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// collectAllFuncUnits - Construct a map of function unit names to bits.
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//
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int collectAllFuncUnits(std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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int &maxResources,
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raw_ostream &OS);
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//
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// collectAllComboFuncs - Construct a map from a combo function unit bit to
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// the bits of all included functional units.
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//
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int collectAllComboFuncs(std::vector<Record*> &ComboFuncList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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raw_ostream &OS);
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//
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// collectOneInsnClass - Populate allInsnClasses with one instruction class.
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//
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int collectOneInsnClass(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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Record *ItinData,
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raw_ostream &OS);
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//
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// collectAllInsnClasses - Populate allInsnClasses which is a set of units
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// used in each stage.
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//
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int collectAllInsnClasses(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::vector<Record*> &ItinDataList,
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int &maxStages,
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raw_ostream &OS);
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// Emit code for a subset of itineraries.
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void emitForItineraries(raw_ostream &OS,
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std::vector<Record *> &ProcItinList,
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std::string DFAName);
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void run(raw_ostream &OS);
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};
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} // end anonymous namespace
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#ifndef NDEBUG
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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//
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// dbgsInsnClass - When debugging, print instruction class stages.
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//
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void dbgsInsnClass(const std::vector<unsigned> &InsnClass) {
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LLVM_DEBUG(dbgs() << "InsnClass: ");
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for (unsigned i = 0; i < InsnClass.size(); ++i) {
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if (i > 0) {
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LLVM_DEBUG(dbgs() << ", ");
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}
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LLVM_DEBUG(dbgs() << "0x" << Twine::utohexstr(InsnClass[i]));
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}
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DFAInput InsnInput = getDFAInsnInput(InsnClass);
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LLVM_DEBUG(dbgs() << " (input: 0x" << Twine::utohexstr(InsnInput) << ")");
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}
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//
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// dbgsIndent - When debugging, indent by the specified amount.
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//
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void dbgsIndent(unsigned indent) {
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for (unsigned i = 0; i < indent; ++i) {
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LLVM_DEBUG(dbgs() << " ");
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}
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}
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#endif // NDEBUG
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DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
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TargetName(CodeGenTarget(R).getName()), Records(R) {}
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//
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// collectAllFuncUnits - Construct a map of function unit names to bits.
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//
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int DFAPacketizerEmitter::collectAllFuncUnits(
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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int &maxFUs,
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raw_ostream &OS) {
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LLVM_DEBUG(dbgs() << "-------------------------------------------------------"
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"----------------------\n");
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LLVM_DEBUG(dbgs() << "collectAllFuncUnits");
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LLVM_DEBUG(dbgs() << " (" << ProcItinList.size() << " itineraries)\n");
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int totalFUs = 0;
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// Parse functional units for all the itineraries.
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for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
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Record *Proc = ProcItinList[i];
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std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
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LLVM_DEBUG(dbgs() << " FU:" << i << " (" << FUs.size() << " FUs) "
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<< Proc->getName());
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// Convert macros to bits for each stage.
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unsigned numFUs = FUs.size();
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for (unsigned j = 0; j < numFUs; ++j) {
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assert ((j < DFA_MAX_RESOURCES) &&
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"Exceeded maximum number of representable resources");
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unsigned FuncResources = (unsigned) (1U << j);
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FUNameToBitsMap[FUs[j]->getName()] = FuncResources;
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LLVM_DEBUG(dbgs() << " " << FUs[j]->getName() << ":0x"
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<< Twine::utohexstr(FuncResources));
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}
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if (((int) numFUs) > maxFUs) {
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maxFUs = numFUs;
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}
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totalFUs += numFUs;
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LLVM_DEBUG(dbgs() << "\n");
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}
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return totalFUs;
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}
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//
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// collectAllComboFuncs - Construct a map from a combo function unit bit to
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// the bits of all included functional units.
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//
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int DFAPacketizerEmitter::collectAllComboFuncs(
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std::vector<Record*> &ComboFuncList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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raw_ostream &OS) {
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LLVM_DEBUG(dbgs() << "-------------------------------------------------------"
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"----------------------\n");
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LLVM_DEBUG(dbgs() << "collectAllComboFuncs");
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LLVM_DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
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int numCombos = 0;
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for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
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Record *Func = ComboFuncList[i];
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std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD");
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LLVM_DEBUG(dbgs() << " CFD:" << i << " (" << FUs.size() << " combo FUs) "
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<< Func->getName() << "\n");
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// Convert macros to bits for each stage.
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for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
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assert ((j < DFA_MAX_RESOURCES) &&
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"Exceeded maximum number of DFA resources");
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Record *FuncData = FUs[j];
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Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
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const std::vector<Record*> &FuncList =
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FuncData->getValueAsListOfDefs("FuncList");
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const std::string &ComboFuncName = ComboFunc->getName();
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unsigned ComboBit = FUNameToBitsMap[ComboFuncName];
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unsigned ComboResources = ComboBit;
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LLVM_DEBUG(dbgs() << " combo: " << ComboFuncName << ":0x"
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<< Twine::utohexstr(ComboResources) << "\n");
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for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
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std::string FuncName = FuncList[k]->getName();
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unsigned FuncResources = FUNameToBitsMap[FuncName];
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LLVM_DEBUG(dbgs() << " " << FuncName << ":0x"
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<< Twine::utohexstr(FuncResources) << "\n");
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ComboResources |= FuncResources;
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}
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ComboBitToBitsMap[ComboBit] = ComboResources;
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numCombos++;
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LLVM_DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
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<< Twine::utohexstr(ComboBit) << " = 0x"
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<< Twine::utohexstr(ComboResources) << "\n");
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}
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}
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return numCombos;
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}
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//
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// collectOneInsnClass - Populate allInsnClasses with one instruction class
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//
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int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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Record *ItinData,
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raw_ostream &OS) {
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const std::vector<Record*> &StageList =
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ItinData->getValueAsListOfDefs("Stages");
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// The number of stages.
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unsigned NStages = StageList.size();
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LLVM_DEBUG(dbgs() << " " << ItinData->getValueAsDef("TheClass")->getName()
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<< "\n");
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std::vector<unsigned> UnitBits;
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// Compute the bitwise or of each unit used in this stage.
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for (unsigned i = 0; i < NStages; ++i) {
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const Record *Stage = StageList[i];
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// Get unit list.
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const std::vector<Record*> &UnitList =
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Stage->getValueAsListOfDefs("Units");
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LLVM_DEBUG(dbgs() << " stage:" << i << " [" << UnitList.size()
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<< " units]:");
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unsigned dbglen = 26; // cursor after stage dbgs
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// Compute the bitwise or of each unit used in this stage.
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unsigned UnitBitValue = 0;
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for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
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// Conduct bitwise or.
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std::string UnitName = UnitList[j]->getName();
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LLVM_DEBUG(dbgs() << " " << j << ":" << UnitName);
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dbglen += 3 + UnitName.length();
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assert(FUNameToBitsMap.count(UnitName));
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UnitBitValue |= FUNameToBitsMap[UnitName];
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}
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if (UnitBitValue != 0)
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UnitBits.push_back(UnitBitValue);
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while (dbglen <= 64) { // line up bits dbgs
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dbglen += 8;
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LLVM_DEBUG(dbgs() << "\t");
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}
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LLVM_DEBUG(dbgs() << " (bits: 0x" << Twine::utohexstr(UnitBitValue)
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<< ")\n");
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}
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if (!UnitBits.empty())
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allInsnClasses.push_back(UnitBits);
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LLVM_DEBUG({
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dbgs() << " ";
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dbgsInsnClass(UnitBits);
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dbgs() << "\n";
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});
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return NStages;
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}
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//
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// collectAllInsnClasses - Populate allInsnClasses which is a set of units
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// used in each stage.
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//
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int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::vector<Record*> &ItinDataList,
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int &maxStages,
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raw_ostream &OS) {
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// Collect all instruction classes.
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unsigned M = ItinDataList.size();
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int numInsnClasses = 0;
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LLVM_DEBUG(dbgs() << "-------------------------------------------------------"
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"----------------------\n"
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<< "collectAllInsnClasses " << ProcName << " (" << M
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<< " classes)\n");
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// Collect stages for each instruction class for all itinerary data
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for (unsigned j = 0; j < M; j++) {
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Record *ItinData = ItinDataList[j];
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int NStages = collectOneInsnClass(ProcName, ProcItinList,
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FUNameToBitsMap, ItinData, OS);
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if (NStages > maxStages) {
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maxStages = NStages;
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}
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numInsnClasses++;
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}
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return numInsnClasses;
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}
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//
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// Run the worklist algorithm to generate the DFA.
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//
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void DFAPacketizerEmitter::run(raw_ostream &OS) {
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OS << "\n"
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<< "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
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OS << "namespace llvm {\n";
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OS << "\n// Input format:\n";
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OS << "#define DFA_MAX_RESTERMS " << DFA_MAX_RESTERMS
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<< "\t// maximum AND'ed resource terms\n";
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OS << "#define DFA_MAX_RESOURCES " << DFA_MAX_RESOURCES
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<< "\t// maximum resource bits in one term\n";
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// Collect processor iteraries.
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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std::unordered_map<std::string, std::vector<Record*>> ItinsByNamespace;
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for (Record *R : ProcItinList)
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ItinsByNamespace[R->getValueAsString("PacketizerNamespace")].push_back(R);
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for (auto &KV : ItinsByNamespace)
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emitForItineraries(OS, KV.second, KV.first);
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OS << "} // end namespace llvm\n";
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}
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void DFAPacketizerEmitter::emitForItineraries(
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raw_ostream &OS, std::vector<Record *> &ProcItinList,
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std::string DFAName) {
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//
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// Collect the Functional units.
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//
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std::map<std::string, unsigned> FUNameToBitsMap;
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int maxResources = 0;
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collectAllFuncUnits(ProcItinList,
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FUNameToBitsMap, maxResources, OS);
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//
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// Collect the Combo Functional units.
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//
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std::map<unsigned, unsigned> ComboBitToBitsMap;
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std::vector<Record*> ComboFuncList =
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Records.getAllDerivedDefinitions("ComboFuncUnits");
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collectAllComboFuncs(ComboFuncList, FUNameToBitsMap, ComboBitToBitsMap, OS);
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//
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// Collect the itineraries.
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//
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int maxStages = 0;
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int numInsnClasses = 0;
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for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
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Record *Proc = ProcItinList[i];
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// Get processor itinerary name.
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const std::string &ProcName = Proc->getName();
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// Skip default.
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if (ProcName == "NoItineraries")
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continue;
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// Sanity check for at least one instruction itinerary class.
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unsigned NItinClasses =
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Records.getAllDerivedDefinitions("InstrItinClass").size();
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if (NItinClasses == 0)
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return;
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// Get itinerary data list.
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std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
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// Collect all instruction classes
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numInsnClasses += collectAllInsnClasses(ProcName, ProcItinList,
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FUNameToBitsMap, ItinDataList, maxStages, OS);
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}
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// The type of a state in the nondeterministic automaton we're defining.
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using NfaStateTy = unsigned;
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// Given a resource state, return all resource states by applying
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// InsnClass.
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auto applyInsnClass = [&](ArrayRef<unsigned> InsnClass,
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NfaStateTy State) -> std::deque<unsigned> {
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std::deque<unsigned> V(1, State);
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// Apply every stage in the class individually.
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for (unsigned Stage : InsnClass) {
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// Apply this stage to every existing member of V in turn.
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size_t Sz = V.size();
|
|
for (unsigned I = 0; I < Sz; ++I) {
|
|
unsigned S = V.front();
|
|
V.pop_front();
|
|
|
|
// For this stage, state combination, try all possible resources.
|
|
for (unsigned J = 0; J < DFA_MAX_RESOURCES; ++J) {
|
|
unsigned ResourceMask = 1U << J;
|
|
if ((ResourceMask & Stage) == 0)
|
|
// This resource isn't required by this stage.
|
|
continue;
|
|
unsigned Combo = ComboBitToBitsMap[ResourceMask];
|
|
if (Combo && ((~S & Combo) != Combo))
|
|
// This combo units bits are not available.
|
|
continue;
|
|
unsigned ResultingResourceState = S | ResourceMask | Combo;
|
|
if (ResultingResourceState == S)
|
|
continue;
|
|
V.push_back(ResultingResourceState);
|
|
}
|
|
}
|
|
}
|
|
return V;
|
|
};
|
|
|
|
// Given a resource state, return a quick (conservative) guess as to whether
|
|
// InsnClass can be applied. This is a filter for the more heavyweight
|
|
// applyInsnClass.
|
|
auto canApplyInsnClass = [](ArrayRef<unsigned> InsnClass,
|
|
NfaStateTy State) -> bool {
|
|
for (unsigned Resources : InsnClass) {
|
|
if ((State | Resources) == State)
|
|
return false;
|
|
}
|
|
return true;
|
|
};
|
|
|
|
DfaEmitter Emitter;
|
|
std::deque<NfaStateTy> Worklist(1, 0);
|
|
std::set<NfaStateTy> SeenStates;
|
|
SeenStates.insert(Worklist.front());
|
|
while (!Worklist.empty()) {
|
|
NfaStateTy State = Worklist.front();
|
|
Worklist.pop_front();
|
|
for (unsigned i = 0; i < allInsnClasses.size(); i++) {
|
|
const std::vector<unsigned> &InsnClass = allInsnClasses[i];
|
|
if (!canApplyInsnClass(InsnClass, State))
|
|
continue;
|
|
for (unsigned NewState : applyInsnClass(InsnClass, State)) {
|
|
if (SeenStates.emplace(NewState).second)
|
|
Worklist.emplace_back(NewState);
|
|
Emitter.addTransition(State, NewState, getDFAInsnInput(InsnClass));
|
|
}
|
|
}
|
|
}
|
|
|
|
OS << "} // end namespace llvm\n\n";
|
|
OS << "namespace {\n";
|
|
std::string TargetAndDFAName = TargetName + DFAName;
|
|
Emitter.emit(TargetAndDFAName, OS);
|
|
OS << "} // end anonymous namespace\n\n";
|
|
|
|
std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
|
|
OS << "namespace llvm {\n";
|
|
OS << "DFAPacketizer *" << SubTargetClassName << "::"
|
|
<< "create" << DFAName
|
|
<< "DFAPacketizer(const InstrItineraryData *IID) const {\n"
|
|
<< " Automaton<uint64_t> A(ArrayRef<" << TargetAndDFAName
|
|
<< "Transition>(" << TargetAndDFAName << "Transitions), "
|
|
<< TargetAndDFAName << "TransitionInfo);\n"
|
|
<< " return new DFAPacketizer(IID, std::move(A));\n"
|
|
<< "\n}\n\n";
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
|
|
emitSourceFileHeader("Target DFA Packetizer Tables", OS);
|
|
DFAPacketizerEmitter(RK).run(OS);
|
|
}
|
|
|
|
} // end namespace llvm
|