Djordje Todorovic 5048a0858b [RISCV] Generate MIPS load/store pair instructions (#124717) ...

Introduce RISCVLoadStoreOptimizer MIR Pass that will do the
optimization. The load/store pairing pass identifies adjacent load/store
instructions operating on consecutive memory locations and merges them
into a single paired instruction.

This is part of MIPS extensions for the p8700 CPU.

Production of ldp/sdp instructions is OFF by default, since it is
beneficial for -Os only in the case of p8700 CPU.

2025-03-07 09:21:36 +01:00

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