Krzysztof Drewniak 554859c736 [TTI] Make isLegalMasked{Load,Store} take an address space (#134006) ...

In order to facilitate targets that only support masked loads/stores
on certain address spaces (AMDGPU will support them in an upcoming
patch, but only for address space 7), add an AddressSpace parameter
to isLegalMaskedLoad and isLegalMaskedStore

2025-04-02 15:38:10 -05:00

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AsmParser

[VE] Rename VariantKind to Specifier and clean up code

2025-03-20 21:04:11 -07:00

Disassembler

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MCTargetDesc

MCValue: add setSpecifier to simplify code

2025-03-23 12:36:46 -07:00

TargetInfo

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CMakeLists.txt

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LVLGen.cpp

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VE.h

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VE.td

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VEAsmPrinter.cpp

[VE] Rename VariantKind to Specifier and clean up code

2025-03-20 21:04:11 -07:00

VECallingConv.td

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VECustomDAG.cpp

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VECustomDAG.h

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VEFrameLowering.cpp

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VEFrameLowering.h

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VEInstrBuilder.h

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VEInstrFormats.td

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VEInstrInfo.cpp

[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)

2025-02-24 09:55:34 -08:00

VEInstrInfo.h

[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)

2025-02-24 09:55:34 -08:00

VEInstrInfo.td

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VEInstrIntrinsicVL.gen.td

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VEInstrIntrinsicVL.td

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VEInstrPatternsVec.td

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VEInstrVec.td

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VEISelDAGToDAG.cpp

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VEISelLowering.cpp

[Target] Use DenseSet instead of DenseMap (NFC) (#132619)

2025-03-23 11:05:33 -07:00

VEISelLowering.h

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VEMachineFunctionInfo.cpp

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VEMachineFunctionInfo.h

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VEMCInstLower.cpp

[VE] Rename VariantKind to Specifier and clean up code

2025-03-20 21:04:11 -07:00

VERegisterInfo.cpp

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VERegisterInfo.h

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VERegisterInfo.td

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VESubtarget.cpp

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VESubtarget.h

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VETargetMachine.cpp

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VETargetMachine.h

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VETargetTransformInfo.h

[TTI] Make isLegalMasked{Load,Store} take an address space (#134006)

2025-04-02 15:38:10 -05:00

VVPInstrInfo.td

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VVPInstrPatternsVec.td

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VVPISelLowering.cpp

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VVPNodes.def

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