Files
clang-p2996/llvm/test/CodeGen/ARM/fast-isel-br-phi.ll
Jim Grosbach 667b147dba ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

llvm-svn: 189274
2013-08-26 20:22:05 +00:00

1.5 KiB