28ddbd4a86
In PR #79382, I need to add a new type that derives from ConstantArrayType. This means that ConstantArrayType can no longer use `llvm::TrailingObjects` to store the trailing optional Expr*. This change refactors ConstantArrayType to store a 60-bit integer and 4-bits for the integer size in bytes. This replaces the APInt field previously in the type but preserves enough information to recreate it where needed. To reduce the number of places where the APInt is re-constructed I've also added some helper methods to the ConstantArrayType to allow some common use cases that operate on either the stored small integer or the APInt as appropriate. Resolves #85124.
814 lines
30 KiB
C++
814 lines
30 KiB
C++
//===- ARM.cpp ------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ABIInfoImpl.h"
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#include "TargetInfo.h"
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using namespace clang;
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using namespace clang::CodeGen;
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//===----------------------------------------------------------------------===//
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// ARM ABI Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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class ARMABIInfo : public ABIInfo {
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ARMABIKind Kind;
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bool IsFloatABISoftFP;
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public:
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ARMABIInfo(CodeGenTypes &CGT, ARMABIKind Kind) : ABIInfo(CGT), Kind(Kind) {
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setCCs();
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IsFloatABISoftFP = CGT.getCodeGenOpts().FloatABI == "softfp" ||
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CGT.getCodeGenOpts().FloatABI == ""; // default
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}
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bool isEABI() const {
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switch (getTarget().getTriple().getEnvironment()) {
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case llvm::Triple::Android:
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case llvm::Triple::EABI:
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case llvm::Triple::EABIHF:
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case llvm::Triple::GNUEABI:
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case llvm::Triple::GNUEABIHF:
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case llvm::Triple::MuslEABI:
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case llvm::Triple::MuslEABIHF:
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return true;
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default:
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return getTarget().getTriple().isOHOSFamily();
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}
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}
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bool isEABIHF() const {
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switch (getTarget().getTriple().getEnvironment()) {
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case llvm::Triple::EABIHF:
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case llvm::Triple::GNUEABIHF:
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case llvm::Triple::MuslEABIHF:
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return true;
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default:
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return false;
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}
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}
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ARMABIKind getABIKind() const { return Kind; }
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bool allowBFloatArgsAndRet() const override {
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return !IsFloatABISoftFP && getTarget().hasBFloat16Type();
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}
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private:
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ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic,
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unsigned functionCallConv) const;
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ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic,
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unsigned functionCallConv) const;
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ABIArgInfo classifyHomogeneousAggregate(QualType Ty, const Type *Base,
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uint64_t Members) const;
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ABIArgInfo coerceIllegalVector(QualType Ty) const;
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bool isIllegalVectorType(QualType Ty) const;
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bool containsAnyFP16Vectors(QualType Ty) const;
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bool isHomogeneousAggregateBaseType(QualType Ty) const override;
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bool isHomogeneousAggregateSmallEnough(const Type *Ty,
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uint64_t Members) const override;
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bool isZeroLengthBitfieldPermittedInHomogeneousAggregate() const override;
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bool isEffectivelyAAPCS_VFP(unsigned callConvention, bool acceptHalf) const;
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void computeInfo(CGFunctionInfo &FI) const override;
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Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
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QualType Ty) const override;
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llvm::CallingConv::ID getLLVMDefaultCC() const;
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llvm::CallingConv::ID getABIDefaultCC() const;
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void setCCs();
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};
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class ARMSwiftABIInfo : public SwiftABIInfo {
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public:
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explicit ARMSwiftABIInfo(CodeGenTypes &CGT)
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: SwiftABIInfo(CGT, /*SwiftErrorInRegister=*/true) {}
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bool isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
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unsigned NumElts) const override;
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};
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class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
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public:
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ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIKind K)
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: TargetCodeGenInfo(std::make_unique<ARMABIInfo>(CGT, K)) {
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SwiftInfo = std::make_unique<ARMSwiftABIInfo>(CGT);
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}
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int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
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return 13;
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}
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StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
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return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
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}
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bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const override {
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llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
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// 0-15 are the 16 integer registers.
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AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
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return false;
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}
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unsigned getSizeOfUnwindException() const override {
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if (getABIInfo<ARMABIInfo>().isEABI())
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return 88;
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return TargetCodeGenInfo::getSizeOfUnwindException();
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}
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void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
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CodeGen::CodeGenModule &CGM) const override {
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if (GV->isDeclaration())
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return;
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const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
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if (!FD)
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return;
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auto *Fn = cast<llvm::Function>(GV);
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if (const auto *TA = FD->getAttr<TargetAttr>()) {
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ParsedTargetAttr Attr =
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CGM.getTarget().parseTargetAttr(TA->getFeaturesStr());
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if (!Attr.BranchProtection.empty()) {
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TargetInfo::BranchProtectionInfo BPI;
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StringRef DiagMsg;
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StringRef Arch =
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Attr.CPU.empty() ? CGM.getTarget().getTargetOpts().CPU : Attr.CPU;
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if (!CGM.getTarget().validateBranchProtection(Attr.BranchProtection,
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Arch, BPI, DiagMsg)) {
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CGM.getDiags().Report(
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D->getLocation(),
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diag::warn_target_unsupported_branch_protection_attribute)
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<< Arch;
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} else {
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Fn->addFnAttr("sign-return-address", BPI.getSignReturnAddrStr());
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Fn->addFnAttr("branch-target-enforcement",
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BPI.BranchTargetEnforcement ? "true" : "false");
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}
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} else if (CGM.getLangOpts().BranchTargetEnforcement ||
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CGM.getLangOpts().hasSignReturnAddress()) {
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// If the Branch Protection attribute is missing, validate the target
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// Architecture attribute against Branch Protection command line
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// settings.
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if (!CGM.getTarget().isBranchProtectionSupportedArch(Attr.CPU))
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CGM.getDiags().Report(
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D->getLocation(),
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diag::warn_target_unsupported_branch_protection_attribute)
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<< Attr.CPU;
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}
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}
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const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
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if (!Attr)
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return;
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const char *Kind;
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switch (Attr->getInterrupt()) {
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case ARMInterruptAttr::Generic: Kind = ""; break;
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case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
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case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
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case ARMInterruptAttr::SWI: Kind = "SWI"; break;
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case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
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case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
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}
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Fn->addFnAttr("interrupt", Kind);
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ARMABIKind ABI = getABIInfo<ARMABIInfo>().getABIKind();
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if (ABI == ARMABIKind::APCS)
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return;
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// AAPCS guarantees that sp will be 8-byte aligned on any public interface,
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// however this is not necessarily true on taking any interrupt. Instruct
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// the backend to perform a realignment as part of the function prologue.
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llvm::AttrBuilder B(Fn->getContext());
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B.addStackAlignmentAttr(8);
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Fn->addFnAttrs(B);
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}
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};
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class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
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public:
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WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIKind K)
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: ARMTargetCodeGenInfo(CGT, K) {}
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void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
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CodeGen::CodeGenModule &CGM) const override;
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void getDependentLibraryOption(llvm::StringRef Lib,
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llvm::SmallString<24> &Opt) const override {
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Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
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}
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void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
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llvm::SmallString<32> &Opt) const override {
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Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
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}
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};
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void WindowsARMTargetCodeGenInfo::setTargetAttributes(
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const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
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ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
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if (GV->isDeclaration())
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return;
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addStackProbeTargetAttributes(D, GV, CGM);
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}
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}
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void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
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if (!::classifyReturnType(getCXXABI(), FI, *this))
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FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), FI.isVariadic(),
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FI.getCallingConvention());
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for (auto &I : FI.arguments())
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I.info = classifyArgumentType(I.type, FI.isVariadic(),
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FI.getCallingConvention());
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// Always honor user-specified calling convention.
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if (FI.getCallingConvention() != llvm::CallingConv::C)
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return;
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llvm::CallingConv::ID cc = getRuntimeCC();
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if (cc != llvm::CallingConv::C)
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FI.setEffectiveCallingConvention(cc);
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}
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/// Return the default calling convention that LLVM will use.
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llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
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// The default calling convention that LLVM will infer.
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if (isEABIHF() || getTarget().getTriple().isWatchABI())
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return llvm::CallingConv::ARM_AAPCS_VFP;
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else if (isEABI())
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return llvm::CallingConv::ARM_AAPCS;
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else
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return llvm::CallingConv::ARM_APCS;
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}
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/// Return the calling convention that our ABI would like us to use
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/// as the C calling convention.
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llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
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switch (getABIKind()) {
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case ARMABIKind::APCS:
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return llvm::CallingConv::ARM_APCS;
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case ARMABIKind::AAPCS:
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return llvm::CallingConv::ARM_AAPCS;
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case ARMABIKind::AAPCS_VFP:
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return llvm::CallingConv::ARM_AAPCS_VFP;
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case ARMABIKind::AAPCS16_VFP:
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return llvm::CallingConv::ARM_AAPCS_VFP;
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}
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llvm_unreachable("bad ABI kind");
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}
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void ARMABIInfo::setCCs() {
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assert(getRuntimeCC() == llvm::CallingConv::C);
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// Don't muddy up the IR with a ton of explicit annotations if
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// they'd just match what LLVM will infer from the triple.
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llvm::CallingConv::ID abiCC = getABIDefaultCC();
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if (abiCC != getLLVMDefaultCC())
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RuntimeCC = abiCC;
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}
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ABIArgInfo ARMABIInfo::coerceIllegalVector(QualType Ty) const {
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uint64_t Size = getContext().getTypeSize(Ty);
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if (Size <= 32) {
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llvm::Type *ResType =
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llvm::Type::getInt32Ty(getVMContext());
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return ABIArgInfo::getDirect(ResType);
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}
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if (Size == 64 || Size == 128) {
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auto *ResType = llvm::FixedVectorType::get(
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llvm::Type::getInt32Ty(getVMContext()), Size / 32);
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return ABIArgInfo::getDirect(ResType);
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}
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return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
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}
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ABIArgInfo ARMABIInfo::classifyHomogeneousAggregate(QualType Ty,
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const Type *Base,
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uint64_t Members) const {
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assert(Base && "Base class should be set for homogeneous aggregate");
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// Base can be a floating-point or a vector.
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if (const VectorType *VT = Base->getAs<VectorType>()) {
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// FP16 vectors should be converted to integer vectors
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if (!getTarget().hasLegalHalfType() && containsAnyFP16Vectors(Ty)) {
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uint64_t Size = getContext().getTypeSize(VT);
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auto *NewVecTy = llvm::FixedVectorType::get(
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llvm::Type::getInt32Ty(getVMContext()), Size / 32);
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llvm::Type *Ty = llvm::ArrayType::get(NewVecTy, Members);
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return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
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}
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}
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unsigned Align = 0;
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if (getABIKind() == ARMABIKind::AAPCS ||
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getABIKind() == ARMABIKind::AAPCS_VFP) {
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// For alignment adjusted HFAs, cap the argument alignment to 8, leave it
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// default otherwise.
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Align = getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity();
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unsigned BaseAlign = getContext().getTypeAlignInChars(Base).getQuantity();
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Align = (Align > BaseAlign && Align >= 8) ? 8 : 0;
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}
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return ABIArgInfo::getDirect(nullptr, 0, nullptr, false, Align);
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}
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ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic,
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unsigned functionCallConv) const {
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// 6.1.2.1 The following argument types are VFP CPRCs:
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// A single-precision floating-point type (including promoted
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// half-precision types); A double-precision floating-point type;
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// A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
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// with a Base Type of a single- or double-precision floating-point type,
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// 64-bit containerized vectors or 128-bit containerized vectors with one
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// to four Elements.
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// Variadic functions should always marshal to the base standard.
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bool IsAAPCS_VFP =
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!isVariadic && isEffectivelyAAPCS_VFP(functionCallConv, /* AAPCS16 */ false);
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Ty = useFirstFieldIfTransparentUnion(Ty);
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// Handle illegal vector types here.
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if (isIllegalVectorType(Ty))
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return coerceIllegalVector(Ty);
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if (!isAggregateTypeForABI(Ty)) {
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// Treat an enum type as its underlying type.
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if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
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Ty = EnumTy->getDecl()->getIntegerType();
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}
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if (const auto *EIT = Ty->getAs<BitIntType>())
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if (EIT->getNumBits() > 64)
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return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
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return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
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: ABIArgInfo::getDirect());
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}
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if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
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return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
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}
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// Ignore empty records.
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if (isEmptyRecord(getContext(), Ty, true))
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return ABIArgInfo::getIgnore();
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if (IsAAPCS_VFP) {
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// Homogeneous Aggregates need to be expanded when we can fit the aggregate
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// into VFP registers.
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const Type *Base = nullptr;
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uint64_t Members = 0;
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if (isHomogeneousAggregate(Ty, Base, Members))
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return classifyHomogeneousAggregate(Ty, Base, Members);
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} else if (getABIKind() == ARMABIKind::AAPCS16_VFP) {
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// WatchOS does have homogeneous aggregates. Note that we intentionally use
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// this convention even for a variadic function: the backend will use GPRs
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// if needed.
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const Type *Base = nullptr;
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uint64_t Members = 0;
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if (isHomogeneousAggregate(Ty, Base, Members)) {
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assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
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llvm::Type *Ty =
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llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
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return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
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}
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}
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if (getABIKind() == ARMABIKind::AAPCS16_VFP &&
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getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
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// WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
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// bigger than 128-bits, they get placed in space allocated by the caller,
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// and a pointer is passed.
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return ABIArgInfo::getIndirect(
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CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
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}
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// Support byval for ARM.
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// The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
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// most 8-byte. We realign the indirect argument if type alignment is bigger
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// than ABI alignment.
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uint64_t ABIAlign = 4;
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uint64_t TyAlign;
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if (getABIKind() == ARMABIKind::AAPCS_VFP ||
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getABIKind() == ARMABIKind::AAPCS) {
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TyAlign = getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity();
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ABIAlign = std::clamp(TyAlign, (uint64_t)4, (uint64_t)8);
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} else {
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TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
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}
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if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
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assert(getABIKind() != ARMABIKind::AAPCS16_VFP && "unexpected byval");
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return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
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/*ByVal=*/true,
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/*Realign=*/TyAlign > ABIAlign);
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}
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// On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
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// same size and alignment.
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if (getTarget().isRenderScriptTarget()) {
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return coerceToIntArray(Ty, getContext(), getVMContext());
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}
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// Otherwise, pass by coercing to a structure of the appropriate size.
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llvm::Type* ElemTy;
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unsigned SizeRegs;
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// FIXME: Try to match the types of the arguments more accurately where
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// we can.
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if (TyAlign <= 4) {
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ElemTy = llvm::Type::getInt32Ty(getVMContext());
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SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
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} else {
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ElemTy = llvm::Type::getInt64Ty(getVMContext());
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SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
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}
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return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
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}
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static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
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llvm::LLVMContext &VMContext) {
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// APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
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// is called integer-like if its size is less than or equal to one word, and
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// the offset of each of its addressable sub-fields is zero.
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uint64_t Size = Context.getTypeSize(Ty);
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// Check that the type fits in a word.
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if (Size > 32)
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return false;
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// FIXME: Handle vector types!
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if (Ty->isVectorType())
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return false;
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// Float types are never treated as "integer like".
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if (Ty->isRealFloatingType())
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return false;
|
|
|
|
// If this is a builtin or pointer type then it is ok.
|
|
if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
|
|
return true;
|
|
|
|
// Small complex integer types are "integer like".
|
|
if (const ComplexType *CT = Ty->getAs<ComplexType>())
|
|
return isIntegerLikeType(CT->getElementType(), Context, VMContext);
|
|
|
|
// Single element and zero sized arrays should be allowed, by the definition
|
|
// above, but they are not.
|
|
|
|
// Otherwise, it must be a record type.
|
|
const RecordType *RT = Ty->getAs<RecordType>();
|
|
if (!RT) return false;
|
|
|
|
// Ignore records with flexible arrays.
|
|
const RecordDecl *RD = RT->getDecl();
|
|
if (RD->hasFlexibleArrayMember())
|
|
return false;
|
|
|
|
// Check that all sub-fields are at offset 0, and are themselves "integer
|
|
// like".
|
|
const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
|
|
|
|
bool HadField = false;
|
|
unsigned idx = 0;
|
|
for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
|
|
i != e; ++i, ++idx) {
|
|
const FieldDecl *FD = *i;
|
|
|
|
// Bit-fields are not addressable, we only need to verify they are "integer
|
|
// like". We still have to disallow a subsequent non-bitfield, for example:
|
|
// struct { int : 0; int x }
|
|
// is non-integer like according to gcc.
|
|
if (FD->isBitField()) {
|
|
if (!RD->isUnion())
|
|
HadField = true;
|
|
|
|
if (!isIntegerLikeType(FD->getType(), Context, VMContext))
|
|
return false;
|
|
|
|
continue;
|
|
}
|
|
|
|
// Check if this field is at offset 0.
|
|
if (Layout.getFieldOffset(idx) != 0)
|
|
return false;
|
|
|
|
if (!isIntegerLikeType(FD->getType(), Context, VMContext))
|
|
return false;
|
|
|
|
// Only allow at most one field in a structure. This doesn't match the
|
|
// wording above, but follows gcc in situations with a field following an
|
|
// empty structure.
|
|
if (!RD->isUnion()) {
|
|
if (HadField)
|
|
return false;
|
|
|
|
HadField = true;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy, bool isVariadic,
|
|
unsigned functionCallConv) const {
|
|
|
|
// Variadic functions should always marshal to the base standard.
|
|
bool IsAAPCS_VFP =
|
|
!isVariadic && isEffectivelyAAPCS_VFP(functionCallConv, /* AAPCS16 */ true);
|
|
|
|
if (RetTy->isVoidType())
|
|
return ABIArgInfo::getIgnore();
|
|
|
|
if (const VectorType *VT = RetTy->getAs<VectorType>()) {
|
|
// Large vector types should be returned via memory.
|
|
if (getContext().getTypeSize(RetTy) > 128)
|
|
return getNaturalAlignIndirect(RetTy);
|
|
// TODO: FP16/BF16 vectors should be converted to integer vectors
|
|
// This check is similar to isIllegalVectorType - refactor?
|
|
if ((!getTarget().hasLegalHalfType() &&
|
|
(VT->getElementType()->isFloat16Type() ||
|
|
VT->getElementType()->isHalfType())) ||
|
|
(IsFloatABISoftFP &&
|
|
VT->getElementType()->isBFloat16Type()))
|
|
return coerceIllegalVector(RetTy);
|
|
}
|
|
|
|
if (!isAggregateTypeForABI(RetTy)) {
|
|
// Treat an enum type as its underlying type.
|
|
if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
|
|
RetTy = EnumTy->getDecl()->getIntegerType();
|
|
|
|
if (const auto *EIT = RetTy->getAs<BitIntType>())
|
|
if (EIT->getNumBits() > 64)
|
|
return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
|
|
|
|
return isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
|
|
: ABIArgInfo::getDirect();
|
|
}
|
|
|
|
// Are we following APCS?
|
|
if (getABIKind() == ARMABIKind::APCS) {
|
|
if (isEmptyRecord(getContext(), RetTy, false))
|
|
return ABIArgInfo::getIgnore();
|
|
|
|
// Complex types are all returned as packed integers.
|
|
//
|
|
// FIXME: Consider using 2 x vector types if the back end handles them
|
|
// correctly.
|
|
if (RetTy->isAnyComplexType())
|
|
return ABIArgInfo::getDirect(llvm::IntegerType::get(
|
|
getVMContext(), getContext().getTypeSize(RetTy)));
|
|
|
|
// Integer like structures are returned in r0.
|
|
if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
|
|
// Return in the smallest viable integer type.
|
|
uint64_t Size = getContext().getTypeSize(RetTy);
|
|
if (Size <= 8)
|
|
return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
|
|
if (Size <= 16)
|
|
return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
|
|
return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
|
|
}
|
|
|
|
// Otherwise return in memory.
|
|
return getNaturalAlignIndirect(RetTy);
|
|
}
|
|
|
|
// Otherwise this is an AAPCS variant.
|
|
|
|
if (isEmptyRecord(getContext(), RetTy, true))
|
|
return ABIArgInfo::getIgnore();
|
|
|
|
// Check for homogeneous aggregates with AAPCS-VFP.
|
|
if (IsAAPCS_VFP) {
|
|
const Type *Base = nullptr;
|
|
uint64_t Members = 0;
|
|
if (isHomogeneousAggregate(RetTy, Base, Members))
|
|
return classifyHomogeneousAggregate(RetTy, Base, Members);
|
|
}
|
|
|
|
// Aggregates <= 4 bytes are returned in r0; other aggregates
|
|
// are returned indirectly.
|
|
uint64_t Size = getContext().getTypeSize(RetTy);
|
|
if (Size <= 32) {
|
|
// On RenderScript, coerce Aggregates <= 4 bytes to an integer array of
|
|
// same size and alignment.
|
|
if (getTarget().isRenderScriptTarget()) {
|
|
return coerceToIntArray(RetTy, getContext(), getVMContext());
|
|
}
|
|
if (getDataLayout().isBigEndian())
|
|
// Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
|
|
return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
|
|
|
|
// Return in the smallest viable integer type.
|
|
if (Size <= 8)
|
|
return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
|
|
if (Size <= 16)
|
|
return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
|
|
return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
|
|
} else if (Size <= 128 && getABIKind() == ARMABIKind::AAPCS16_VFP) {
|
|
llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
|
|
llvm::Type *CoerceTy =
|
|
llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
|
|
return ABIArgInfo::getDirect(CoerceTy);
|
|
}
|
|
|
|
return getNaturalAlignIndirect(RetTy);
|
|
}
|
|
|
|
/// isIllegalVector - check whether Ty is an illegal vector type.
|
|
bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
|
|
if (const VectorType *VT = Ty->getAs<VectorType> ()) {
|
|
// On targets that don't support half, fp16 or bfloat, they are expanded
|
|
// into float, and we don't want the ABI to depend on whether or not they
|
|
// are supported in hardware. Thus return false to coerce vectors of these
|
|
// types into integer vectors.
|
|
// We do not depend on hasLegalHalfType for bfloat as it is a
|
|
// separate IR type.
|
|
if ((!getTarget().hasLegalHalfType() &&
|
|
(VT->getElementType()->isFloat16Type() ||
|
|
VT->getElementType()->isHalfType())) ||
|
|
(IsFloatABISoftFP &&
|
|
VT->getElementType()->isBFloat16Type()))
|
|
return true;
|
|
if (isAndroid()) {
|
|
// Android shipped using Clang 3.1, which supported a slightly different
|
|
// vector ABI. The primary differences were that 3-element vector types
|
|
// were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
|
|
// accepts that legacy behavior for Android only.
|
|
// Check whether VT is legal.
|
|
unsigned NumElements = VT->getNumElements();
|
|
// NumElements should be power of 2 or equal to 3.
|
|
if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
|
|
return true;
|
|
} else {
|
|
// Check whether VT is legal.
|
|
unsigned NumElements = VT->getNumElements();
|
|
uint64_t Size = getContext().getTypeSize(VT);
|
|
// NumElements should be power of 2.
|
|
if (!llvm::isPowerOf2_32(NumElements))
|
|
return true;
|
|
// Size should be greater than 32 bits.
|
|
return Size <= 32;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// Return true if a type contains any 16-bit floating point vectors
|
|
bool ARMABIInfo::containsAnyFP16Vectors(QualType Ty) const {
|
|
if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
|
|
uint64_t NElements = AT->getZExtSize();
|
|
if (NElements == 0)
|
|
return false;
|
|
return containsAnyFP16Vectors(AT->getElementType());
|
|
} else if (const RecordType *RT = Ty->getAs<RecordType>()) {
|
|
const RecordDecl *RD = RT->getDecl();
|
|
|
|
// If this is a C++ record, check the bases first.
|
|
if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
|
|
if (llvm::any_of(CXXRD->bases(), [this](const CXXBaseSpecifier &B) {
|
|
return containsAnyFP16Vectors(B.getType());
|
|
}))
|
|
return true;
|
|
|
|
if (llvm::any_of(RD->fields(), [this](FieldDecl *FD) {
|
|
return FD && containsAnyFP16Vectors(FD->getType());
|
|
}))
|
|
return true;
|
|
|
|
return false;
|
|
} else {
|
|
if (const VectorType *VT = Ty->getAs<VectorType>())
|
|
return (VT->getElementType()->isFloat16Type() ||
|
|
VT->getElementType()->isBFloat16Type() ||
|
|
VT->getElementType()->isHalfType());
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool ARMSwiftABIInfo::isLegalVectorType(CharUnits VectorSize, llvm::Type *EltTy,
|
|
unsigned NumElts) const {
|
|
if (!llvm::isPowerOf2_32(NumElts))
|
|
return false;
|
|
unsigned size = CGT.getDataLayout().getTypeStoreSizeInBits(EltTy);
|
|
if (size > 64)
|
|
return false;
|
|
if (VectorSize.getQuantity() != 8 &&
|
|
(VectorSize.getQuantity() != 16 || NumElts == 1))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
|
|
// Homogeneous aggregates for AAPCS-VFP must have base types of float,
|
|
// double, or 64-bit or 128-bit vectors.
|
|
if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
|
|
if (BT->getKind() == BuiltinType::Float ||
|
|
BT->getKind() == BuiltinType::Double ||
|
|
BT->getKind() == BuiltinType::LongDouble)
|
|
return true;
|
|
} else if (const VectorType *VT = Ty->getAs<VectorType>()) {
|
|
unsigned VecSize = getContext().getTypeSize(VT);
|
|
if (VecSize == 64 || VecSize == 128)
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
|
|
uint64_t Members) const {
|
|
return Members <= 4;
|
|
}
|
|
|
|
bool ARMABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate() const {
|
|
// AAPCS32 says that the rule for whether something is a homogeneous
|
|
// aggregate is applied to the output of the data layout decision. So
|
|
// anything that doesn't affect the data layout also does not affect
|
|
// homogeneity. In particular, zero-length bitfields don't stop a struct
|
|
// being homogeneous.
|
|
return true;
|
|
}
|
|
|
|
bool ARMABIInfo::isEffectivelyAAPCS_VFP(unsigned callConvention,
|
|
bool acceptHalf) const {
|
|
// Give precedence to user-specified calling conventions.
|
|
if (callConvention != llvm::CallingConv::C)
|
|
return (callConvention == llvm::CallingConv::ARM_AAPCS_VFP);
|
|
else
|
|
return (getABIKind() == ARMABIKind::AAPCS_VFP) ||
|
|
(acceptHalf && (getABIKind() == ARMABIKind::AAPCS16_VFP));
|
|
}
|
|
|
|
Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
|
|
QualType Ty) const {
|
|
CharUnits SlotSize = CharUnits::fromQuantity(4);
|
|
|
|
// Empty records are ignored for parameter passing purposes.
|
|
if (isEmptyRecord(getContext(), Ty, true)) {
|
|
VAListAddr = VAListAddr.withElementType(CGF.Int8PtrTy);
|
|
auto *Load = CGF.Builder.CreateLoad(VAListAddr);
|
|
return Address(Load, CGF.ConvertTypeForMem(Ty), SlotSize);
|
|
}
|
|
|
|
CharUnits TySize = getContext().getTypeSizeInChars(Ty);
|
|
CharUnits TyAlignForABI = getContext().getTypeUnadjustedAlignInChars(Ty);
|
|
|
|
// Use indirect if size of the illegal vector is bigger than 16 bytes.
|
|
bool IsIndirect = false;
|
|
const Type *Base = nullptr;
|
|
uint64_t Members = 0;
|
|
if (TySize > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
|
|
IsIndirect = true;
|
|
|
|
// ARMv7k passes structs bigger than 16 bytes indirectly, in space
|
|
// allocated by the caller.
|
|
} else if (TySize > CharUnits::fromQuantity(16) &&
|
|
getABIKind() == ARMABIKind::AAPCS16_VFP &&
|
|
!isHomogeneousAggregate(Ty, Base, Members)) {
|
|
IsIndirect = true;
|
|
|
|
// Otherwise, bound the type's ABI alignment.
|
|
// The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
|
|
// APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
|
|
// Our callers should be prepared to handle an under-aligned address.
|
|
} else if (getABIKind() == ARMABIKind::AAPCS_VFP ||
|
|
getABIKind() == ARMABIKind::AAPCS) {
|
|
TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
|
|
TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
|
|
} else if (getABIKind() == ARMABIKind::AAPCS16_VFP) {
|
|
// ARMv7k allows type alignment up to 16 bytes.
|
|
TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
|
|
TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
|
|
} else {
|
|
TyAlignForABI = CharUnits::fromQuantity(4);
|
|
}
|
|
|
|
TypeInfoChars TyInfo(TySize, TyAlignForABI, AlignRequirementKind::None);
|
|
return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
|
|
SlotSize, /*AllowHigherAlign*/ true);
|
|
}
|
|
|
|
std::unique_ptr<TargetCodeGenInfo>
|
|
CodeGen::createARMTargetCodeGenInfo(CodeGenModule &CGM, ARMABIKind Kind) {
|
|
return std::make_unique<ARMTargetCodeGenInfo>(CGM.getTypes(), Kind);
|
|
}
|
|
|
|
std::unique_ptr<TargetCodeGenInfo>
|
|
CodeGen::createWindowsARMTargetCodeGenInfo(CodeGenModule &CGM, ARMABIKind K) {
|
|
return std::make_unique<WindowsARMTargetCodeGenInfo>(CGM.getTypes(), K);
|
|
}
|