6afda56faa
Instead of caching STI in the RISCVELFTargetStreamer, store the two flags we need from it. My goal is to allow RISCVAsmPrinter to override these flags using IR module metadata for LTO. So they need to be separated from the STI used to construct the TargetStreamer. This patch should be NFC as long as no one is changing the contents of the STI that was used to construct the TargetStreamer between the constructor and the use of the flags.
155 lines
5.2 KiB
C++
155 lines
5.2 KiB
C++
//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides RISC-V specific target streamer methods.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetStreamer.h"
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#include "RISCVBaseInfo.h"
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#include "RISCVMCTargetDesc.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/RISCVAttributes.h"
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#include "llvm/Support/RISCVISAInfo.h"
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using namespace llvm;
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RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
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void RISCVTargetStreamer::finish() { finishAttributeSection(); }
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void RISCVTargetStreamer::reset() {}
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void RISCVTargetStreamer::emitDirectiveOptionPush() {}
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void RISCVTargetStreamer::emitDirectiveOptionPop() {}
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void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
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void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
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void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
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void RISCVTargetStreamer::emitDirectiveOptionArch(
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ArrayRef<RISCVOptionArchArg> Args) {}
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void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
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void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
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void RISCVTargetStreamer::finishAttributeSection() {}
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void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
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StringRef String) {}
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void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
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unsigned IntValue,
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StringRef StringValue) {}
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void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
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assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
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TargetABI = ABI;
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}
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void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
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HasRVC = STI.hasFeature(RISCV::FeatureStdExtC) ||
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STI.hasFeature(RISCV::FeatureStdExtZca);
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HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso);
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}
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void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
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bool EmitStackAlign) {
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if (EmitStackAlign) {
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unsigned StackAlign;
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if (TargetABI == RISCVABI::ABI_ILP32E)
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StackAlign = 4;
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else if (TargetABI == RISCVABI::ABI_LP64E)
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StackAlign = 8;
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else
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StackAlign = 16;
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emitAttribute(RISCVAttrs::STACK_ALIGN, StackAlign);
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}
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auto ParseResult = RISCVFeatures::parseFeatureBits(
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STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
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if (!ParseResult) {
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report_fatal_error(ParseResult.takeError());
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} else {
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auto &ISAInfo = *ParseResult;
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emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
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}
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}
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// This part is for ascii assembly output
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RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS)
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: RISCVTargetStreamer(S), OS(OS) {}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
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OS << "\t.option\tpush\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
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OS << "\t.option\tpop\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
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OS << "\t.option\tpic\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
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OS << "\t.option\tnopic\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
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OS << "\t.option\trvc\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
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OS << "\t.option\tnorvc\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
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OS << "\t.option\trelax\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
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OS << "\t.option\tnorelax\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
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ArrayRef<RISCVOptionArchArg> Args) {
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OS << "\t.option\tarch";
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for (const auto &Arg : Args) {
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OS << ", ";
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switch (Arg.Type) {
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case RISCVOptionArchArgType::Full:
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break;
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case RISCVOptionArchArgType::Plus:
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OS << "+";
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break;
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case RISCVOptionArchArgType::Minus:
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OS << "-";
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break;
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}
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OS << Arg.Value;
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}
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OS << "\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
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OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
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}
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void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
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OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
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}
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void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
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StringRef String) {
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OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
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}
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void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
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unsigned IntValue,
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StringRef StringValue) {}
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void RISCVTargetAsmStreamer::finishAttributeSection() {}
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