a65ccc1b9f
On processors supporting vector registers and SIMD instructions, enable i128 as legal type in VRs. This allows many operations to be implemented via native instructions directly in VRs (including add, subtract, logical operations and shifts). For a few other operations (e.g. multiply and divide, as well as atomic operations), we need to move the i128 value back to a GPR pair to use the corresponding instruction there. Overall, this is still beneficial. The patch includes the following LLVM changes: - Enable i128 as legal type - Set up legal operations (in SystemZInstrVector.td) - Custom expansion for i128 add/subtract with carry - Custom expansion for i128 comparisons and selects - Support for moving i128 to/from GPR pairs when required - Handle 128-bit integer constant values everywhere - Use i128 as intrinsic operand type where appropriate - Updated and new test cases In addition, clang builtins are updated to reflect the intrinsic operand type changes (which also improves compatibility with GCC).
309 lines
14 KiB
TableGen
309 lines
14 KiB
TableGen
//=- SystemZCallingConv.td - Calling conventions for SystemZ -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for the SystemZ ABI.
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//===----------------------------------------------------------------------===//
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class CCIfExtend<CCAction A>
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: CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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class CCIfSubtarget<string F, CCAction A>
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: CCIf<!strconcat("static_cast<const SystemZSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).", F),
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A>;
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// Match if this specific argument is a fixed (i.e. named) argument.
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class CCIfFixed<CCAction A>
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: CCIf<"static_cast<SystemZCCState *>(&State)->IsFixed(ValNo)", A>;
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// Match if this specific argument is not a fixed (i.e. vararg) argument.
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class CCIfNotFixed<CCAction A>
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: CCIf<"!(static_cast<SystemZCCState *>(&State)->IsFixed(ValNo))", A>;
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// Match if this specific argument was widened from a short vector type.
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class CCIfShortVector<CCAction A>
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: CCIf<"static_cast<SystemZCCState *>(&State)->IsShortVector(ValNo)", A>;
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//===----------------------------------------------------------------------===//
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// z/Linux return value calling convention
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//===----------------------------------------------------------------------===//
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def RetCC_SystemZ_ELF : CallingConv<[
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// Promote i32 to i64 if it has an explicit extension type.
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CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
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// A SwiftError is returned in R9.
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CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R9D]>>>,
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// ABI-compliant code returns 64-bit integers in R2. Make the other
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// call-clobbered argument registers available for code that doesn't
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// care about the ABI. (R6 is an argument register too, but is
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// call-saved and therefore not suitable for return values.)
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CCIfType<[i32], CCAssignToReg<[R2L, R3L, R4L, R5L]>>,
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CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D]>>,
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// ABI-complaint code returns float and double in F0. Make the
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// other floating-point argument registers available for code that
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// doesn't care about the ABI. All floating-point argument registers
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// are call-clobbered, so we can use all of them here.
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CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
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CCIfType<[f64], CCAssignToReg<[F0D, F2D, F4D, F6D]>>,
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// Similarly for vectors, with V24 being the ABI-compliant choice.
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// Sub-128 vectors are returned in the same way, but they're widened
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// to one of these types during type legalization.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[V24, V26, V28, V30, V25, V27, V29, V31]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// z/Linux argument calling conventions for GHC
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//===----------------------------------------------------------------------===//
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def CC_SystemZ_GHC : CallingConv<[
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// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, R8, SpLim
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CCIfType<[i64], CCAssignToReg<[R7D, R8D, R10D, R11D, R12D, R13D,
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R6D, R2D, R3D, R4D, R5D, R9D]>>,
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// Pass in STG registers: F1, ..., F6
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CCIfType<[f32], CCAssignToReg<[F8S, F9S, F10S, F11S, F0S, F1S]>>,
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// Pass in STG registers: D1, ..., D6
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CCIfType<[f64], CCAssignToReg<[F12D, F13D, F14D, F15D, F2D, F3D]>>,
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// Pass in STG registers: XMM1, ..., XMM6
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfFixed<CCAssignToReg<[V16, V17, V18, V19, V20, V21]>>>>,
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// Fail otherwise
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CCCustom<"CC_SystemZ_GHC_Error">
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]>;
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//===----------------------------------------------------------------------===//
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// z/Linux argument calling conventions
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//===----------------------------------------------------------------------===//
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def CC_SystemZ_ELF : CallingConv<[
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CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_SystemZ_GHC>>,
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// Promote i32 to i64 if it has an explicit extension type.
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// The convention is that true integer arguments that are smaller
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// than 64 bits should be marked as extended, but structures that
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// are smaller than 64 bits shouldn't.
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CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
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// A SwiftSelf is passed in callee-saved R10.
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CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R10D]>>>,
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// A SwiftError is passed in callee-saved R9.
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CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R9D]>>>,
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// Force i128 (if the type is legal) and long double values to the stack
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// and pass i64 pointers to them.
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CCIfType<[i128, f128], CCPassIndirect<i64>>,
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// If i128 is not legal, such values are already split into two i64 here,
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// so we have to use a custom handler.
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CCIfType<[i64], CCCustom<"CC_SystemZ_I128Indirect">>,
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// The first 5 integer arguments are passed in R2-R6. Note that R6
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// is call-saved.
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CCIfType<[i32], CCAssignToReg<[R2L, R3L, R4L, R5L, R6L]>>,
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CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>,
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// The first 4 float and double arguments are passed in even registers F0-F6.
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CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
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CCIfType<[f64], CCAssignToReg<[F0D, F2D, F4D, F6D]>>,
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// The first 8 named vector arguments are passed in V24-V31. Sub-128 vectors
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// are passed in the same way, but they're widened to one of these types
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// during type legalization.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfFixed<CCAssignToReg<[V24, V26, V28, V30,
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V25, V27, V29, V31]>>>>,
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// However, sub-128 vectors which need to go on the stack occupy just a
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// single 8-byte-aligned 8-byte stack slot. Pass as i64.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfShortVector<CCBitConvertToType<i64>>>>,
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// Other vector arguments are passed in 8-byte-aligned 16-byte stack slots.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToStack<16, 8>>>,
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// Other arguments are passed in 8-byte-aligned 8-byte stack slots.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
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]>;
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//===----------------------------------------------------------------------===//
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// z/Linux callee-saved registers
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//===----------------------------------------------------------------------===//
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def CSR_SystemZ_ELF : CalleeSavedRegs<(add (sequence "R%dD", 6, 15),
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(sequence "F%dD", 8, 15))>;
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// R9 is used to return SwiftError; remove it from CSR.
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def CSR_SystemZ_SwiftError : CalleeSavedRegs<(sub CSR_SystemZ_ELF, R9D)>;
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// "All registers" as used by the AnyReg calling convention.
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// Note that registers 0 and 1 are still defined as intra-call scratch
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// registers that may be clobbered e.g. by PLT stubs.
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def CSR_SystemZ_AllRegs : CalleeSavedRegs<(add (sequence "R%dD", 2, 15),
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(sequence "F%dD", 0, 15))>;
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def CSR_SystemZ_AllRegs_Vector : CalleeSavedRegs<(add (sequence "R%dD", 2, 15),
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(sequence "V%d", 0, 31))>;
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def CSR_SystemZ_NoRegs : CalleeSavedRegs<(add)>;
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//===----------------------------------------------------------------------===//
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// z/OS XPLINK64 callee-saved registers
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//===----------------------------------------------------------------------===//
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def CSR_SystemZ_XPLINK64 : CalleeSavedRegs<(add (sequence "R%dD", 8, 15),
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(sequence "F%dD", 15, 8))>;
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def CSR_SystemZ_XPLINK64_Vector : CalleeSavedRegs<(add CSR_SystemZ_XPLINK64,
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(sequence "V%d", 23, 16))>;
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//===----------------------------------------------------------------------===//
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// z/OS XPLINK64 return value calling convention
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//===----------------------------------------------------------------------===//
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def RetCC_SystemZ_XPLINK64 : CallingConv<[
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// XPLINK64 ABI compliant code widens integral types smaller than i64
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// to i64.
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CCIfType<[i32], CCPromoteToType<i64>>,
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// Structs of size 1-24 bytes are returned in R1D, R2D, and R3D.
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CCIfType<[i64], CCIfInReg<CCAssignToReg<[R1D, R2D, R3D]>>>,
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// An i64 is returned in R3D. R2D and R1D provided for ABI non-compliant
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// code.
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CCIfType<[i64], CCAssignToReg<[R3D, R2D, R1D]>>,
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// ABI compliant code returns floating point values in FPR0, FPR2, FPR4
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// and FPR6, using as many registers as required.
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// All floating point return-value registers are call-clobbered.
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CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
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CCIfType<[f64], CCAssignToReg<[F0D, F2D, F4D, F6D]>>,
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// ABI compliant code returns f128 in F0D and F2D, hence F0Q.
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// F4D and F6D, hence F4Q are used for complex long double types.
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CCIfType<[f128], CCAssignToReg<[F0Q,F4Q]>>,
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// ABI compliant code returns vectors in VR24 but other registers
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// are provided for code that does not care about the ABI.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[V24, V25, V26, V27, V28, V29, V30, V31]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// z/OS XPLINK64 argument calling conventions
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//===----------------------------------------------------------------------===//
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// XPLink uses a logical argument list consisting of contiguous register-size
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// words (8 bytes in 64-Bit mode) where some arguments are passed in registers
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// and some in storage.
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// Even though 3 GPRs, 4 FPRs, and 8 VRs may be used,
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// space must be reserved for all the args on stack.
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// The first three register-sized words of the parameter area are passed in
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// GPRs 1-3. FP values and vector-type arguments are instead passed in FPRs
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// and VRs respectively, but if a FP value or vector argument occupies one of
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// the first three register-sized words of the parameter area, the corresponding
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// GPR's value is not used to pass arguments.
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//
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// The XPLINK64 Calling Convention is fully specified in Chapter 22 of the z/OS
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// Language Environment Vendor Interfaces. Appendix B of the same document contains
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// examples.
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def CC_SystemZ_XPLINK64 : CallingConv<[
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// XPLINK64 ABI compliant code widens integral types smaller than i64
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// to i64 before placing the parameters either on the stack or in registers.
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CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
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// Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRs.
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// Although we assign the f32 vararg to be bitcast, it will first be promoted
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// to an f64 within convertValVTToLocVT().
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CCIfType<[f32, f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
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// long double, can only be passed in GPR2 and GPR3, if available,
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// hence R2Q
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CCIfType<[f128], CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>,
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// Non fixed vector arguments are treated in the same way as long
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// doubles.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>>,
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// A SwiftSelf is passed in callee-saved R10.
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CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R10D]>>>,
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// A SwiftError is passed in R0.
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CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R0D]>>>,
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// Force i128 values to the stack and pass i64 pointers to them.
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CCIfType<[i128], CCPassIndirect<i64>>,
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// If i128 is not legal, such values are already split into two i64 here,
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// so we have to use a custom handler.
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CCIfType<[i64], CCCustom<"CC_SystemZ_I128Indirect">>,
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// The first 3 integer arguments are passed in registers R1D-R3D.
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// The rest will be passed in the user area. The address offset of the user
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// area can be found in register R4D.
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CCIfType<[i64], CCAssignToRegAndStack<[R1D, R2D, R3D], 8, 8>>,
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// The first 8 named vector arguments are passed in V24-V31. Sub-128 vectors
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// are passed in the same way, but they're widened to one of these types
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// during type legalization.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>>,
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfFixed<CCAssignToRegAndStack<[V24, V25, V26, V27,
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V28, V29, V30, V31], 16, 8>>>>,
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// The first 4 named float and double arguments are passed in registers
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// FPR0-FPR6. The rest will be passed in the user area.
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CCIfType<[f32, f64], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>,
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CCIfType<[f32], CCIfFixed<CCAssignToRegAndStack<[F0S, F2S, F4S, F6S], 4, 8>>>,
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CCIfType<[f64], CCIfFixed<CCAssignToRegAndStack<[F0D, F2D, F4D, F6D], 8, 8>>>,
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// The first 2 long double arguments are passed in register FPR0/FPR2
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// and FPR4/FPR6. The rest will be passed in the user area.
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CCIfType<[f128], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>,
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CCIfType<[f128], CCIfFixed<CCAssignToRegAndStack<[F0Q, F4Q], 16, 8>>>,
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// Other arguments are passed in 8-byte-aligned 8-byte stack slots.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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// Other f128 arguments are passed in 8-byte-aligned 16-byte stack slots.
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CCIfType<[f128], CCAssignToStack<16, 8>>,
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// Vector arguments are passed in 8-byte-alinged 16-byte stack slots too.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToStack<16, 8>>>
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]>;
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//===----------------------------------------------------------------------===//
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// s390x return value calling convention
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//===----------------------------------------------------------------------===//
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def RetCC_SystemZ : CallingConv<[
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// zOS XPLINK64
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CCIfSubtarget<"isTargetXPLINK64()", CCDelegateTo<RetCC_SystemZ_XPLINK64>>,
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// ELF Linux SystemZ
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CCIfSubtarget<"isTargetELF()", CCDelegateTo<RetCC_SystemZ_ELF>>
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]>;
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//===----------------------------------------------------------------------===//
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// s390x argument calling conventions
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//===----------------------------------------------------------------------===//
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def CC_SystemZ : CallingConv<[
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// zOS XPLINK64
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CCIfSubtarget<"isTargetXPLINK64()", CCDelegateTo<CC_SystemZ_XPLINK64>>,
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// ELF Linux SystemZ
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CCIfSubtarget<"isTargetELF()", CCDelegateTo<CC_SystemZ_ELF>>
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]>;
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