XChy 313a33b9df [InstCombine] Reduce nested logical operator if poison is implied (#86823) ...

Fixes #76623
Alive2 proof: https://alive2.llvm.org/ce/z/gX6znJ (I'm not sure how to
write a proof for such transform, maybe there are mistakes)

In most cases, `icmp(a, C1) && (other_cond && icmp(a, C2))` will be
reduced to `icmp(a, C1) & (other_cond && icmp(a, C2))`, since latter
icmp always implies the poison of the former. After reduction, it's
easier to simplify the icmp chain.
Similarly, this patch does the same thing for `(A && B) && C --> A && (B
& C)`. Maybe we could constraint such reduction only on icmps if there
is regression in benchmarks.

2024-04-10 14:19:44 +08:00

..

CMakeLists.txt

…

InstCombineAddSub.cpp

[LLVM] Remove nuw neg (#86295)

2024-03-26 20:56:16 +08:00

InstCombineAndOrXor.cpp

[LLVM] Remove nuw neg (#86295)

2024-03-26 20:56:16 +08:00

InstCombineAtomicRMW.cpp

…

InstCombineCalls.cpp

[LLVM] Remove nuw neg (#86295)

2024-03-26 20:56:16 +08:00

InstCombineCasts.cpp

[InstCombine] Remove the canonicalization of trunc to i1 (#84628)

2024-03-29 21:47:35 +08:00

InstCombineCompares.cpp

[InstCombine] fold (icmp eq/ne (or disjoint x, C0), C1) -> (icmp eq/ne x, C0^C1)

2024-04-09 15:38:18 -05:00

InstCombineInternal.h

[RemoveDIs][NFC] Rename DPValue -> DbgVariableRecord (#85216)

2024-03-19 20:07:07 +00:00

InstCombineLoadStoreAlloca.cpp

[NFC][RemoveDIs] Insert instruction using iterators in Transforms/

2024-03-05 15:12:22 +00:00

InstCombineMulDivRem.cpp

[InstCombine] add restrict reassoc for the powi(X,Y) / X

2024-03-27 16:47:03 +08:00

InstCombineNegator.cpp

[LLVM] Remove nuw neg (#86295)

2024-03-26 20:56:16 +08:00

InstCombinePHI.cpp

[NFC][RemoveDIs] Insert instruction using iterators in Transforms/

2024-03-05 15:12:22 +00:00

InstCombineSelect.cpp

[InstCombine] Reduce nested logical operator if poison is implied (#86823)

2024-04-10 14:19:44 +08:00

InstCombineShifts.cpp

[InstCombine] integrate N{U,S}WAddLike into existing folds

2024-03-21 13:03:38 -05:00

InstCombineSimplifyDemanded.cpp

[InstCombine] Remove shl if we only demand known signbits of shift source (#79014)

2024-04-10 11:19:09 +09:00

InstCombineVectorOps.cpp

[InstCombine] Copy flags of extractelement for extelt -> icmp combine (#86366)

2024-03-24 16:14:56 +01:00

InstructionCombining.cpp

[RemoveDIs][NFC] Rename DPValue -> DbgVariableRecord (#85216)

2024-03-19 20:07:07 +00:00