2861ec84fc
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
158 lines
4.5 KiB
YAML
158 lines
4.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: BITv8i8_v2s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1, $d2
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; CHECK-LABEL: name: BITv8i8_v2s32
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; CHECK: liveins: $d0, $d1, $d2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %lhs:fpr64 = COPY $d0
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; CHECK-NEXT: %mhs:fpr64 = COPY $d1
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; CHECK-NEXT: %rhs:fpr64 = COPY $d2
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; CHECK-NEXT: %bit:fpr64 = BSPv8i8 %lhs, %mhs, %rhs
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; CHECK-NEXT: $d0 = COPY %bit
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%lhs:fpr(<2 x s32>) = COPY $d0
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%mhs:fpr(<2 x s32>) = COPY $d1
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%rhs:fpr(<2 x s32>) = COPY $d2
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%bit:fpr(<2 x s32>) = G_BSP %lhs, %mhs, %rhs
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$d0 = COPY %bit(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: BITv8i8_v4s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1, $d2
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; CHECK-LABEL: name: BITv8i8_v4s16
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; CHECK: liveins: $d0, $d1, $d2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %lhs:fpr64 = COPY $d0
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; CHECK-NEXT: %mhs:fpr64 = COPY $d1
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; CHECK-NEXT: %rhs:fpr64 = COPY $d2
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; CHECK-NEXT: %bit:fpr64 = BSPv8i8 %lhs, %mhs, %rhs
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; CHECK-NEXT: $d0 = COPY %bit
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%lhs:fpr(<4 x s16>) = COPY $d0
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%mhs:fpr(<4 x s16>) = COPY $d1
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%rhs:fpr(<4 x s16>) = COPY $d2
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%bit:fpr(<4 x s16>) = G_BSP %lhs, %mhs, %rhs
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$d0 = COPY %bit(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: BITv16i8_v2s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; CHECK-LABEL: name: BITv16i8_v2s64
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; CHECK: liveins: $q0, $q1, $q2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %lhs:fpr128 = COPY $q0
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; CHECK-NEXT: %mhs:fpr128 = COPY $q1
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; CHECK-NEXT: %rhs:fpr128 = COPY $q2
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; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
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; CHECK-NEXT: $q0 = COPY %bit
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%lhs:fpr(<2 x s64>) = COPY $q0
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%mhs:fpr(<2 x s64>) = COPY $q1
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%rhs:fpr(<2 x s64>) = COPY $q2
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%bit:fpr(<2 x s64>) = G_BSP %lhs, %mhs, %rhs
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$q0 = COPY %bit(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: BITv16i8_v4s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; CHECK-LABEL: name: BITv16i8_v4s32
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; CHECK: liveins: $q0, $q1, $q2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %lhs:fpr128 = COPY $q0
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; CHECK-NEXT: %mhs:fpr128 = COPY $q1
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; CHECK-NEXT: %rhs:fpr128 = COPY $q2
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; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
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; CHECK-NEXT: $q0 = COPY %bit
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%lhs:fpr(<4 x s32>) = COPY $q0
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%mhs:fpr(<4 x s32>) = COPY $q1
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%rhs:fpr(<4 x s32>) = COPY $q2
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%bit:fpr(<4 x s32>) = G_BSP %lhs, %mhs, %rhs
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$q0 = COPY %bit(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: BITv16i8_v8s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; CHECK-LABEL: name: BITv16i8_v8s16
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; CHECK: liveins: $q0, $q1, $q2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %lhs:fpr128 = COPY $q0
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; CHECK-NEXT: %mhs:fpr128 = COPY $q1
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; CHECK-NEXT: %rhs:fpr128 = COPY $q2
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; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
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; CHECK-NEXT: $q0 = COPY %bit
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%lhs:fpr(<8 x s16>) = COPY $q0
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%mhs:fpr(<8 x s16>) = COPY $q1
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%rhs:fpr(<8 x s16>) = COPY $q2
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%bit:fpr(<8 x s16>) = G_BSP %lhs, %mhs, %rhs
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$q0 = COPY %bit(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: BITv16i8_v16s8
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; CHECK-LABEL: name: BITv16i8_v16s8
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; CHECK: liveins: $q0, $q1, $q2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %lhs:fpr128 = COPY $q0
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; CHECK-NEXT: %mhs:fpr128 = COPY $q1
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; CHECK-NEXT: %rhs:fpr128 = COPY $q2
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; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
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; CHECK-NEXT: $q0 = COPY %bit
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%lhs:fpr(<16 x s8>) = COPY $q0
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%mhs:fpr(<16 x s8>) = COPY $q1
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%rhs:fpr(<16 x s8>) = COPY $q2
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%bit:fpr(<16 x s8>) = G_BSP %lhs, %mhs, %rhs
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$q0 = COPY %bit(<16 x s8>)
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RET_ReallyLR implicit $q0
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