f2c164c815
SIInsertWaitcnts inserts waitcnt instructions to resolve data dependencies. The GFX10+ vscnt (VMEM store count) counter is never used in this way. It is only used to resolve memory dependencies, and that is handled by SIMemoryLegalizer. Hence there is no need to conservatively wait for vscnt to be 0 on function entry and before returns. Differential Revision: https://reviews.llvm.org/D153537
39 lines
1.6 KiB
LLVM
39 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s
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define hidden <2 x i64> @icmp_v2i32_sext_to_v2i64(<2 x i32> %arg) {
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; CHECK-LABEL: icmp_v2i32_sext_to_v2i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
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; CHECK-NEXT: v_bfe_i32 v0, v0, 0, 1
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; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
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; CHECK-NEXT: v_bfe_i32 v2, v1, 0, 1
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; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v2
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%cmp = icmp eq <2 x i32> %arg, zeroinitializer
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%sext = sext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %sext
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}
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define hidden <2 x i64> @icmp_v2i32_zext_to_v2i64(<2 x i32> %arg) {
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; CHECK-LABEL: icmp_v2i32_zext_to_v2i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_mov_b32_e32 v3, 0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
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; CHECK-NEXT: v_and_b32_e32 v2, 1, v1
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%cmp = icmp eq <2 x i32> %arg, zeroinitializer
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%sext = zext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %sext
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}
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