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clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel
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David Green ac321cbb03 [AArch64][GlobalISel] Legalize Insert vector element (#81453) 
This attempts to standardize and extend some of the insert vector
element lowering. Most notably:
- More types are handled by splitting illegal vectors.
- The index type for G_INSERT_VECTOR_ELT is canonicalized to
  TLI.getVectorIdxTy(), similar to extact_vector_element.
- Some of the existing patterns now have the index type specified to
  make sure they can apply to GISel too.
- The C++ selection code has been removed, relying on tablegen patterns.
- G_INSERT_VECTOR_ELT with small GPR input elements are pre-selected to
  use a i32 type, allowing the existing patterns to apply.
- Variable index inserts are lowered in post-legalizer lowering,
  expanding into a stack store and reload.
2024-04-08 08:44:13 +01:00
..
add_shl.ll
…
add.v2i16.ll
AMDGPU: Fix packed 16-bit inline constants (#76522)
2024-01-04 00:10:15 +01:00
add.vni16.ll
…
addo.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
addsubu64.ll
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
amdgpu-irtranslator.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
amdgpu-prelegalizer-combiner-crash.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
andn2.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
artifact-combiner-anyext.mir
…
artifact-combiner-asserts.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
artifact-combiner-build-vector.mir
…
artifact-combiner-concat-vectors.mir
…
artifact-combiner-cse-leaves-dead-cast.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
artifact-combiner-extract.mir
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artifact-combiner-sext.mir
…
artifact-combiner-trunc.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
artifact-combiner-unmerge-values.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
artifact-combiner-zext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
ashr.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
assert-align.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
atomic_load_local.ll
…
atomic_optimizations_mul_one.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
atomic_store_local.ll
…
atomicrmw_udec_wrap.ll
[AMDGPU][SIMemoryLegalizer] Fix order of GL0/1_INV on GFX10/11 (#81450)
2024-02-13 09:07:51 +01:00
atomicrmw_uinc_wrap.ll
[AMDGPU][SIMemoryLegalizer] Fix order of GL0/1_INV on GFX10/11 (#81450)
2024-02-13 09:07:51 +01:00
bitcast_38_i16.ll
[AMDGPU][GlobalIsel] Introduce isRegisterClassType to check for legal types, instead of checking bit width. (#68189)
2024-02-13 08:26:10 +01:00
bool-legalization.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
br-constant-invalid-sgpr-copy.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
bswap.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
buffer-atomic-fadd.f32-rtn.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
buffer-atomic-fadd.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
buffer-atomic-fadd.v2f16-no-rtn.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
buffer-atomic-fadd.v2f16-rtn.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
buffer-schedule.ll
…
bug-legalization-artifact-combiner-dead-def.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
bug-legalization-artifact-combiner-dead-def.mir
…
call-outgoing-stack-args.ll
Revert "[AMDGPU] Compiler should synthesize private buffer resource descriptor from flat_scratch_init" (#81234)
2024-02-09 09:57:38 +01:00
clamp-fmed3-const-combine.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
clamp-minmax-const-combine.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
combine-add-nullptr.mir
…
combine-add-to-ptradd.mir
…
combine-amdgpu-cvt-f32-ubyte.mir
…
combine-ashr-narrow.mir
…
combine-ext-legalizer.mir
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combine-extract-vector-load.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
combine-fabs-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fcanonicalize.mir
AMDGPU: Fix broken denormal constant folding of canonicalize
2023-07-17 19:54:20 -04:00
combine-fdiv-sqrt-to-rsq.mir
[AMDGPU][GlobalISel] Add fdiv / sqrt to rsq combine (#78673)
2024-02-22 09:47:36 +01:00
combine-fma-add-ext-fma.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-add-ext-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-add-fma-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-add-mul-post-legalize.mir
[AArch64][AMDGPU][GlobalISel] Remove vector handling from unmerge_dead_to_trunc (#82224)
2024-02-20 10:54:44 +00:00
combine-fma-add-mul-pre-legalize.mir
[AArch64][AMDGPU][GlobalISel] Remove vector handling from unmerge_dead_to_trunc (#82224)
2024-02-20 10:54:44 +00:00
combine-fma-add-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-sub-ext-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-sub-ext-neg-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-sub-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-sub-neg-mul.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fma-unmerge-values.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fold-binop-into-select.mir
[GlobalIsel] Combine selects with constants (#76089)
2024-01-02 17:26:39 +01:00
combine-foldable-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fpneg-one-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
combine-fsh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-fsub-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-itofp.mir
…
combine-lshr-narrow.mir
…
combine-or-redundant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-redundant-and.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-redundant-neg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-rot.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-rsq.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-rsq.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-sext-inreg.mir
…
combine-shift-imm-chain-illegal-types.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-imm-chain-shlsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-imm-chain.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-of-shifted-logic-shlsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shift-of-shifted-logic.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-shl-from-extend-narrow.postlegal.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shl-from-extend-narrow.prelegal.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
combine-shl-narrow.mir
…
combine-short-clamp.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
combine-trunc-shift.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
combine-urem-pow-2.mir
…
combine-zext-trunc.mir
…
combiner-crash.ll
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compute-num-sign-bits-med3.mir
AMDGPU: Implement known bits functions for min3/max3/med3
2023-06-10 10:58:44 -04:00
constant-bus-restriction.ll
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crash-stack-address-O0.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
cvt_f32_ubyte.ll
…
dereferenceable-declaration.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
divergence-divergent-i1-phis-no-lane-mask-merging.ll
AMDGPU/GlobalISel: lane masks merging (#73337)
2024-02-29 13:57:59 +01:00
divergence-divergent-i1-phis-no-lane-mask-merging.mir
AMDGPU/GlobalISel: lane masks merging (#73337)
2024-02-29 13:57:59 +01:00
divergence-divergent-i1-used-outside-loop.ll
AMDGPU/GlobalISel: lane masks merging (#73337)
2024-02-29 13:57:59 +01:00
divergence-divergent-i1-used-outside-loop.mir
AMDGPU/GlobalISel: lane masks merging (#73337)
2024-02-29 13:57:59 +01:00
divergence-structurizer.ll
AMDGPU/GlobalISel: lane masks merging (#73337)
2024-02-29 13:57:59 +01:00
divergence-structurizer.mir
AMDGPU/GlobalISel: lane masks merging (#73337)
2024-02-29 13:57:59 +01:00
divergence-temporal-divergent-i1.ll
AMDGPU\GlobalISel: remove amdgpu-global-isel-risky-select flag (#83426)
2024-02-29 15:38:54 +01:00
divergence-temporal-divergent-i1.mir
MachineSSAUpdater: use all vreg attributes instead of reg class only (#78431)
2024-02-26 13:46:13 +01:00
divergence-temporal-divergent-reg.ll
AMDGPU\GlobalISel: remove amdgpu-global-isel-risky-select flag (#83426)
2024-02-29 15:38:54 +01:00
divergence-temporal-divergent-reg.mir
AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)
2024-02-05 14:07:01 +01:00
divergent-control-flow.ll
[AMDGPU] Combine or remove redundant waitcnts at the end of each MBB (#87539)
2024-04-04 10:14:16 +01:00
dropped_debug_info_assert.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
dummy-target.ll
…
dynamic-alloca-divergent.ll
…
dynamic-alloca-uniform.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
extractelement-stack-lower.ll
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
extractelement.i8.ll
[GISel] Combine (Scalarize) vector load followed by an element extract.
2023-12-06 11:23:23 +05:30
extractelement.i16.ll
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
extractelement.i128.ll
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
extractelement.ll
[AMDGPU][GlobalIsel] Introduce isRegisterClassType to check for legal types, instead of checking bit width. (#68189)
2024-02-13 08:26:10 +01:00
fdiv.f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fdiv.f32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fdiv.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
flat-atomic-fadd.f32.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
flat-atomic-fadd.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
flat-atomic-fadd.v2f16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
flat-scratch-init.gfx.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
flat-scratch-init.ll
…
flat-scratch.ll
AMDGPU/GFX12: Insert waitcnts before stores with scope_sys (#82996)
2024-02-28 16:18:04 +01:00
floor.f64.ll
…
fma.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmax_legacy.ll
…
fmed3-min-max-const-combine.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
fmin_legacy.ll
…
fmul.v2f16.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
fp64-atomics-gfx90a.ll
[AMDGPU] Support double type in atomic optimizer. (#84307)
2024-03-22 09:25:06 +05:30
fp-atomics-gfx940.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fpow.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
frem.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fshl.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
fshr.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
function-returns.ll
[IRTranslator] Set NUW flag for inbounds gep and load/store offsets
2023-09-22 16:16:28 +02:00
function-returns.v2i65.ll
…
global-atomic-fadd.f32-no-rtn.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
global-atomic-fadd.f64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
global-atomic-fadd.v2f16-no-rtn.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
global-atomic-fadd.v2f16-rtn.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
global-value.illegal.ll
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global-value.ll
[AMDGPU] Tweak handling of GlobalAddress operands in SI_PC_ADD_REL_OFFSET (#70960)
2023-11-01 19:48:30 +00:00
hip.extern.shared.array.ll
…
i1-copy.ll
…
image-waterfall-loop-O0.ll
[AMDGPU] Try to fix the block prologs broken by RA inserted instructions (#69924)
2023-10-27 19:10:18 +05:30
implicit-kernarg-backend-usage-global-isel.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
inline-asm-mismatched-size.ll
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
inline-asm.ll
…
insertelement-stack-lower.ll
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
2024-02-09 09:20:25 +01:00
insertelement.i8.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
insertelement.i16.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
insertelement.large.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
insertelement.ll
[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)
2023-12-14 14:10:27 +01:00
inst-select-abs.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-add.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-add.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.class.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.class.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cos.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cos.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pk.i16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pk.u16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pknorm.i16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pknorm.u16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.cvt.pkrtz.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.ds.swizzle.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.exp.compr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.exp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fcmp.constants.w32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fcmp.constants.w64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fmad.ftz.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fmed3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fmed3.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fract.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.fract.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.groupstaticsize.mir
…
inst-select-amdgcn.mbcnt.lo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.mul.u24.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.mulhi.i24.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.mulhi.u24.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rcp.legacy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rcp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rcp.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.readfirstlane.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.reloc.constant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.clamp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.legacy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.rsq.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.s.barrier.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.s.sendmsg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.sffbh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.sin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgcn.sin.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-atomic-cmpxchg-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-ffbh-u32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-ffbl-b32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-amdgpu-wave-address.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-and.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-anyext.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ashr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ashr.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ashr.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomic-cmpxchg-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomic-cmpxchg-region.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-add-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-add-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-fadd-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-fadd-region.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-xchg-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-atomicrmw-xchg-region.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-bitcast.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-bitreverse.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-br.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-brcond.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
inst-select-bswap.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-build-vector-trunc.v2s16.mir
[GlobalISel] Also set dead flags of implicit defs added by BuildMI
2023-08-11 08:38:37 +02:00
inst-select-build-vector.mir
…
inst-select-concat-vectors.mir
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inst-select-constant.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
inst-select-copy.mir
AMDGPU/GlobalISel: Set dead on scc on manually selected instructions
2023-07-28 14:14:06 -04:00
inst-select-ctlz-zero-undef.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ctpop.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-cttz-zero-undef.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-extract-vector-elt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-extract.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fabs.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-fadd.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fadd.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fadd.s64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fcanonicalize.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fceil.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fceil.s16.mir
[AMDGPU][True16] Support VOP3 source DPP operands. (#80892)
2024-02-08 16:23:00 +00:00
inst-select-fcmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fcmp.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fconstant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fexp2.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ffloor.s16.mir
[AMDGPU][True16] Support VOP3 source DPP operands. (#80892)
2024-02-08 16:23:00 +00:00
inst-select-ffloor.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ffloor.s64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fma.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmad.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmaxnum-ieee.mir
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inst-select-fmaxnum-ieee.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmaxnum-ieee.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmaxnum.mir
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inst-select-fmaxnum.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmaxnum.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fminnum-ieee.mir
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inst-select-fminnum-ieee.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fminnum-ieee.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fminnum.mir
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inst-select-fminnum.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fminnum.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fmul.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fneg.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-fptosi.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-fptoui.mir
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inst-select-fract.f64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-frame-index.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-freeze.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
inst-select-fshr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-i1-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-icmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-icmp.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-icmp.s64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-implicit-def.mir
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inst-select-insert-vector-elt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-insert.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-intrinsic-trunc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-intrinsic-trunc.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-inttoptr.mir
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inst-select-load-atomic-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-atomic-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-atomic-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-constant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-global-saddr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-global.s96.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-local-128.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-private.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-smrd.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-lshr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-lshr.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-lshr.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-mad_64_32.mir
[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX11.5 (#79460)
2024-01-25 16:28:49 +00:00
inst-select-merge-values.mir
…
inst-select-mul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-or.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-pattern-add3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-and-or.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-or3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-smed3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-smed3.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-umed3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-umed3.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-xor3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-phi.mir
AMDGPU\GlobalISel: remove amdgpu-global-isel-risky-select flag (#83426)
2024-02-29 15:38:54 +01:00
inst-select-pseudo-scalar-transcendental.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ptr-add.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ptrmask.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ptrtoint.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-returnaddress.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sbfx.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-scalar-float-sop1.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-scalar-float-sop2.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
inst-select-scalar-float-sopc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-scalar-packed.xfail.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sext-inreg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sext.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-sextload-local.mir
…
inst-select-shl.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-shl.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-shl.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sitofp.mir
…
inst-select-smax.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-smin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-smulh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-stacksave-stackrestore.invalid.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-stacksave-stackrestore.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-atomic-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-atomic-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-global.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-global.s96.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-local.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-private.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sub.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-trunc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-trunc.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uadde.gfx10.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uadde.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uaddo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-ubfx.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-uitofp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-umax.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-umin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-umulh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-unmerge-values.mir
…
inst-select-usube.gfx10.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-usube.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-usubo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-xor.mir
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
inst-select-zext.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-zextload-local.mir
…
irtranslate-bf16.ll
[GlobalISel] Fix buildCopyFromRegs for split vectors (#77448)
2024-01-16 10:04:20 +01:00
irtranslator-amdgcn-cs-chain.ll
[AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (#68186)
2023-11-06 12:30:07 +01:00
irtranslator-amdgcn-sendmsg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-amdgpu_kernel-system-sgprs.ll
…
irtranslator-amdgpu_kernel.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
irtranslator-amdgpu_ps.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-amdgpu_vs.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-assert-align.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-atomicrmw.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-call-abi-attribute-hints.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-call-implicit-args.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-call-non-fixed.ll
Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)
2024-03-26 11:01:08 +01:00
irtranslator-call-return-values.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-call-sret.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-call.ll
Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)
2024-03-26 11:01:08 +01:00
irtranslator-constant-fold-vector-op.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-constantexpr.ll
[IR] Remove FP cast constant expressions (#71408)
2023-11-07 09:34:16 +01:00
irtranslator-constrained-fp.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
irtranslator-fast-math-flags.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-fence.ll
…
irtranslator-fixed-function-abi-vgpr-args.ll
…
irtranslator-function-args.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-function-args.v2i65.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-getelementptr.ll
…
irtranslator-indirect-call.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-inline-asm.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-invariant.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-memory-intrinsics.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-metadata.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
irtranslator-non-integral-address-spaces-vectors.ll
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
irtranslator-non-integral-address-spaces.ll
[AMDGPU] Add IR-level pass to rewrite away address space 7 (#77952)
2024-03-06 09:49:58 -06:00
irtranslator-prefetch.ll
[GlobalISel] Add G_PREFETCH (#74863)
2023-12-11 11:06:50 +00:00
irtranslator-ptrmask.ll
[IR] Require that ptrmask mask matches pointer index size (#69343)
2023-10-24 09:54:29 +02:00
irtranslator-readnone-intrinsic-callsite.ll
…
irtranslator-sat.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
irtranslator-sibling-call.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-struct-return-intrinsics.ll
…
irtranslator-tail-call.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-zext-vec-index.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-global-value.ll
…
lds-misaligned-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-relocs.ll
…
lds-zero-initializer.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-abs.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-add.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-addrspacecast.mir
[AMDGPU] Make a few more tests default COV agnostic (#78926)
2024-01-22 11:22:57 -05:00
legalize-amdgcn.if-invalid.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-amdgcn.if.xfail.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
…
legalize-and.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-anyext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ashr.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-atomic-cmpxchg-with-success.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-atomic-cmpxchg.mir
…
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd-global.mir
…
legalize-atomicrmw-fadd-local.mir
…
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
…
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
…
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-bitreverse.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-block-addr.mir
…
legalize-brcond.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
legalize-bswap.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-build-vector-splat.mir
…
legalize-build-vector-trunc.mir
…
legalize-build-vector.mir
[AMDGPU][GlobalIsel] Introduce isRegisterClassType to check for legal types, instead of checking bit width. (#68189)
2024-02-13 08:26:10 +01:00
legalize-build-vector.s16.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
…
legalize-ctlz-zero-undef.mir
[GlobalISel] Add CTLZ known bits. (#86436)
2024-03-26 09:11:35 +00:00
legalize-ctlz.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ctpop.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-cttz-zero-undef.mir
[GlobalISel] Handle sequences of trunc(sext/zext/anyext...) in artifact combiner
2023-08-04 13:29:49 +02:00
legalize-cttz.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-extract-vector-elt.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
legalize-extract.mir
…
legalize-extractelement-crash.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
legalize-fabs.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fadd.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fcanonicalize.mir
…
legalize-fceil.mir
…
legalize-fcmp-s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-fcmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-fconstant.mir
…
legalize-fcopysign.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fcos.mir
…
legalize-fdiv.mir
AMDGPU: Always use v_rcp_f16 and v_rsq_f16
2023-07-05 16:53:01 -04:00
legalize-fexp2.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fexp.mir
[AMDGPU] Generic lowering for rint and nearbyint (#69596)
2023-11-14 18:49:21 +01:00
legalize-ffloor.mir
…
legalize-flog2.mir
AMDGPU: Use correct lowering for llvm.log2.f32
2023-06-23 08:37:37 -04:00
legalize-flog10.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-flog.mir
AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32
2023-07-05 15:30:35 -04:00
legalize-fma.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fmad.s16.mir
…
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fminnum.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fmul.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fneg.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fpext.mir
…
legalize-fpow.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fpowi.mir
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
legalize-fptosi.mir
…
legalize-fptoui.mir
…
legalize-fptrunc.mir
…
legalize-freeze.mir
…
legalize-fshl.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fshr.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-fsin.mir
…
legalize-fsqrt.mir
AMDGPU: Correctly lower llvm.sqrt.f32
2023-09-12 23:22:54 +03:00
legalize-fsub.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-icmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-implicit-def-s1025.mir
…
legalize-implicit-def.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-insert-vector-elt.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
legalize-insert.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
AMDGPU: Use hex floats instead of ugly bitcasting
2023-07-17 19:54:04 -04:00
legalize-intrinsic-round.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-intrinsic-trunc.mir
…
legalize-inttoptr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-jump-table.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.dim.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-llvm.amdgcn.image.load.2d.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.load.3d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.a16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.image.sample.d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.g16.a16.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.g16.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
legalize-llvm.amdgcn.s.buffer.load.mir
[AMDGPU] CodeGen for SMEM instructions (#75579)
2023-12-15 12:10:33 +01:00
legalize-load-constant-32bit.mir
…
legalize-load-constant.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-load-flat.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-load-global.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-load-local.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-load-memory-metadata.mir
…
legalize-load-private.mir
[AMDGPU] CodeGen for GFX12 VFLAT, VSCRATCH and VGLOBAL instructions (#75493)
2023-12-15 15:01:40 +01:00
legalize-lshr.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-memcpy.mir
…
legalize-memcpyinline.mir
…
legalize-memmove.mir
…
legalize-memset.mir
…
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-mul.mir
[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825)
2024-01-08 19:13:38 +00:00
legalize-or.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-phi.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ptr-add.mir
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
legalize-ptrmask.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ptrtoint.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-rotl-rotr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-sadde.mir
…
legalize-saddo.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-saddsat.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-sbfx.mir
…
legalize-sdiv.mir
…
legalize-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-sext-inreg.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sextload-constant-32bit.mir
…
legalize-sextload-flat.mir
…
legalize-sextload-global.mir
…
legalize-sextload-local.mir
…
legalize-sextload-private.mir
…
legalize-shl.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-shuffle-vector.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-shuffle-vector.s16.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-sitofp.mir
…
legalize-smax.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-smin.mir
[AMDGPU][GlobalISel] Update legalizer for G_ABS, G_SMIN, G_SMAX, G_UMIN, G_UMAX
2023-08-02 12:18:18 +02:00
legalize-smulh.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-smulo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-srem.mir
…
legalize-sshlsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-ssube.mir
…
legalize-ssubo.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-ssubsat.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-store-global.mir
[GlobalISel] Refactor extractParts() (#75223)
2024-01-15 16:40:39 +00:00
legalize-store.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-strict_fsub.mir
…
legalize-sub.mir
…
legalize-trap.mir
[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)
2024-03-23 13:12:44 +01:00
legalize-trunc.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-uadde.mir
…
legalize-uaddo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-uaddsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-ubfx.mir
…
legalize-udiv.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-uitofp.mir
…
legalize-umax.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-umin.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-umulh.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-umulo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-unmerge-values.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-urem.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-ushlsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-usube.mir
…
legalize-usubo.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-usubsat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
legalize-vector-args-gfx7.mir
…
legalize-vector-args-gfx8-plus.mir
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
legalize-xor.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-zext.mir
Reland: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
2023-11-02 00:18:19 +01:00
legalize-zextload-constant-32bit.mir
…
legalize-zextload-flat.mir
…
legalize-zextload-global.mir
…
legalize-zextload-local.mir
…
legalize-zextload-private.mir
…
llvm.abs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.div.fmas.ll
AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)
2024-02-05 14:07:01 +01:00
llvm.amdgcn.div.scale.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.ds.fadd.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.ds.fmax.ll
…
llvm.amdgcn.ds.fmin.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
llvm.amdgcn.end.cf.i32.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.end.cf.i64.ll
…
llvm.amdgcn.fdot2.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.fmul.legacy.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.global.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.global.atomic.fadd.ll
…
llvm.amdgcn.if.break.i32.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
llvm.amdgcn.if.break.i64.ll
…
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.atomic.dim.mir
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.gather4.o.dim.ll
…
llvm.amdgcn.image.getresinfo.a16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.getresinfo.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.1d.d16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.1d.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.2d.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.3d.a16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.3d.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.sample.cd.g16.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.image.store.2d.ll
[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)
2023-12-15 12:40:23 +01:00
llvm.amdgcn.implicit.ptr.buffer.ll
…
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Expose RTZ version of f16 interpolation for gfx11+ (#86614)
2024-04-01 09:48:37 +08:00
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.is.private.ll
[AMDGPU] Combine or remove redundant waitcnts at the end of each MBB (#87539)
2024-04-04 10:14:16 +01:00
llvm.amdgcn.is.shared.ll
[AMDGPU] Combine or remove redundant waitcnts at the end of each MBB (#87539)
2024-04-04 10:14:16 +01:00
llvm.amdgcn.kernarg.segment.ptr.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.make.buffer.rsrc.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mfma.gfx90a.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.queue.ptr.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.raw.buffer.atomic.add.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] CodeGen for 64-bit buffer atomic cmpswap intrinsics (#70475)
2023-10-30 16:44:22 +00:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Allow buffer intrinsics to be marked volatile at the IR level (#77847)
2024-01-12 11:20:01 -06:00
llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[AMDGPU] Allow buffer intrinsics to be marked volatile at the IR level (#77847)
2024-01-12 11:20:01 -06:00
llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.rsq.clamp.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.s.setreg.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.s.sleep.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sbfe.ll
[GlobalISel] Handle div-by-pow2 (#83155)
2024-03-29 12:41:47 -04:00
llvm.amdgcn.sdot2.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sdot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sdot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.set.inactive.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.softwqm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.struct.buffer.atomic.add.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Extend zero initialization of return values for TFE (#85759)
2024-03-25 09:01:46 +00:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Fix broken sign-extended subword buffer load combine (#77470)
2024-01-10 10:50:13 +00:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] CodeGen for 64-bit buffer atomic cmpswap intrinsics (#70475)
2023-10-30 16:44:22 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[AMDGPU] Extend zero initialization of return values for TFE (#85759)
2024-03-25 09:01:46 +00:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.sudot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.sudot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.trig.preop.ll
AMDGPU/GlobalISel: Fix not running -global-isel in global isel test
2024-02-06 14:55:48 +05:30
llvm.amdgcn.ubfe.ll
…
llvm.amdgcn.udot2.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.udot4.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.udot8.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.update.dpp.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.wmma_32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.wmma_64.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.workgroup.id.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.workitem.id.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.wqm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.memcpy.inline.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.memcpy.ll
CodeGen: Expand memory intrinsics in PreISelIntrinsicLowering
2023-06-09 21:04:37 -04:00
llvm.memmove.ll
[GlobalISel][Localizer] Allow localization of a small number of repeated phi uses. (#77566)
2024-01-11 18:57:37 +08:00
llvm.memset.ll
[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)
2023-10-30 08:12:28 -07:00
llvm.powi.ll
AMDGPU: Correctly lower llvm.exp2.f32
2023-07-05 17:23:48 -04:00
load-constant32bit.ll
…
load-constant.96.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
load-local.96.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
load-local.128.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
load-unaligned.ll
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2023-07-19 10:33:11 +01:00
localizer-wrong-insert-point.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
localizer.ll
[GlobalISel][Localizer] Allow localization of a small number of repeated phi uses. (#77566)
2024-01-11 18:57:37 +08:00
lshr.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
memory-legalizer-atomic-fence.ll
[AMDGPU][SIMemoryLegalizer] Fix order of GL0/1_INV on GFX10/11 (#81450)
2024-02-13 09:07:51 +01:00
merge-buffer-stores.ll
[SeperateConstOffsetFromGEP] Handle or disjoint flags (#76997)
2024-01-26 09:56:06 -06:00
minmaxabs.ll
…
mubuf-global.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
mul-known-bits.i64.ll
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171)
2024-03-08 09:39:10 +01:00
mul-known-bits.i64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
mul.ll
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171)
2024-03-08 09:39:10 +01:00
mul.v2i16.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
no-cse-nonlocal-convergent-instrs.mir
…
no-legalize-atomic.mir
…
non-entry-alloca.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
orn2.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
postlegalizer-combiner-buildvector-identities.mir
…
postlegalizer-combiner-divrem.mir
…
postlegalizer-combiner-fcanonicalize.mir
…
postlegalizer-combiner-freeze.mir
…
postlegalizer-combiner-reassoc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
postlegalizer-combiner-sextload-from-sextinreg.mir
…
postlegalizer-combiner-trunc-bitcast-buildvector.mir
…
postlegalizer-combiner-unmerge-undef.mir
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
postlegalizer-combiner-zextload-from-and.mir
…
postlegalizercombiner-and.mir
…
postlegalizercombiner-ashr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-load-and-mask.mir
…
postlegalizercombiner-lshr.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-mul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
postlegalizercombiner-sbfx.mir
…
postlegalizercombiner-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
postlegalizercombiner-shl.mir
GlobalISel: Add constant fold combine for zext/sext/anyext
2023-08-24 08:10:01 -04:00
postlegalizercombiner-ubfx.mir
…
prelegalizer-combiner-divrem.mir
[AMDGPU] Convert tests to opaque pointers (NFC)
2024-02-05 12:42:23 +01:00
prelegalizer-combiner-fptrunc_fpext.mir
…
prelegalizer-combiner-redundant-bitcast.mir
…
prelegalizer-combiner-sext_inreg-to-and.mir
…
regbankcombiner-clamp-fmed3-const.mir
[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)
2023-12-13 13:52:40 +01:00
regbankcombiner-clamp-minmax-const.mir
…
regbankcombiner-fmed3-minmax-const.mir
…
regbankcombiner-smed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankcombiner-umed3.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-abs.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-add.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-add.s32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-add.v2s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn-exp-compr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn-exp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn-s-buffer-load.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ballot.i64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.class.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.cvt.pkrtz.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.div.fmas.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.div.scale.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.append.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.bpermute.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.consume.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.gws.init.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.gws.sema.v.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.ordered.add.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.ordered.swap.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.permute.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ds.swizzle.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.else.32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.else.64.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.fcmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.fmul.legacy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.groupstaticsize.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.icmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.image.load.1d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regbankselect-amdgcn.image.sample.1d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regbankselect-amdgcn.interp.mov.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.interp.p1.f16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.interp.p1.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.interp.p2.f16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.interp.p2.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.kernarg.segment.ptr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.kill.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.lds.direct.load.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.lds.param.load.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.live.mask.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.mfma.gfx90a.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.mfma.gfx940.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.mfma.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.ps.live.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.raw.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.raw.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.readfirstlane.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.readlane.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.s.buffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
regbankselect-amdgcn.s.buffer.load.mir
…
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.s.getpc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.s.getreg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.s.memrealtime.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.s.memtime.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.s.sendmsg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.s.sendmsghalt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.struct.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.buffer.store.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.update.dpp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.wqm.demote.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.wqm.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.wqm.vote.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.writelane.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgcn.wwm.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgpu-ffbh-u32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgpu-ffbl-b32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-amdgpu-wave-address.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-and-s1.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-and.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-anyext.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ashr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-assert-align.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-assert-zext.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomic-cmpxchg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-add.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-and.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-fadd.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-max.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-min.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-or.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-sub.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-umax.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-umin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-xchg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-atomicrmw-xor.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-bitcast.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-bitreverse.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-block-addr.mir
…
regbankselect-brcond.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-bswap.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-build-vector.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-concat-vector.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-constant.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ctlz-zero-undef.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ctpop.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-cttz-zero-undef.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-default.mir
…
regbankselect-dyn-stackalloc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-extract-vector-elt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-extract.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fabs.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fadd.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fcanonicalize.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fceil.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fcmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fexp2.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-flog2.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fma.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fmul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fpext.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fptosi.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fptoui.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fptrunc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-frame-index.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-freeze.mir
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00
regbankselect-fshr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fsqrt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-fsub.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-icmp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-icmp.s16.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-illegal-copy.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-implicit-def.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-insert-vector-elt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-insert.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-intrinsic-trunc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-inttoptr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-load.mir
[AMDGPU] CodeGen for GFX12 8/16-bit SMEM loads (#77633)
2024-01-17 10:28:03 +00:00
regbankselect-lshr.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-mad_64_32.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-merge-values.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-mul.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-or.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-phi-s1.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-phi.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-pseudo-scalar-transcendental.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ptr-add.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ptrmask.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ptrtoint.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-reg-sequence.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sadde.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-salu-float.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sbfx.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sext-inreg.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sext.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sextload.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-shl.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sitofp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-smax.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-smin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-smulh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-split-scalar-load-metadata.mir
[AMDGPU] CodeGen for SMEM instructions (#75579)
2023-12-15 12:10:33 +01:00
regbankselect-ssube.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-sub.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-trunc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-uadde.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-uaddo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-ubfx.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-uitofp.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-umax.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-umin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-umulh.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-uniform-load-noclobber.mir
…
regbankselect-unmerge-values.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-usube.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-usubo.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-waterfall-agpr.mir
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-widen-scalar-loads.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-xor.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-zext.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-zextload.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
saddsat.ll
[GlobalIsel] Combine ADDO (#82927)
2024-03-14 12:45:19 +01:00
sbfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
sdiv.i32.ll
[GlobalISel] Handle div-by-pow2 (#83155)
2024-03-29 12:41:47 -04:00
sdiv.i64.ll
[GlobalISel] Handle div-by-pow2 (#83155)
2024-03-29 12:41:47 -04:00
sdivrem.ll
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171)
2024-03-08 09:39:10 +01:00
select-to-fmin-fmax.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
sext_inreg.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
shader-epilogs.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
shl-ext-reduce.ll
AMDGPU/GlobalISel: Handle mubuf load/store for more types (#68268)
2023-10-05 05:36:16 -07:00
shl.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
shlN_add.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
smed3.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
smrd.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
srem.i32.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
srem.i64.ll
[GlobalIsel] Combine ADDO (#82927)
2024-03-14 12:45:19 +01:00
ssubsat.ll
[GlobalIsel] Combine ADDO (#82927)
2024-03-14 12:45:19 +01:00
store-local.96.ll
…
store-local.128.ll
…
strict_fma.f16.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f32.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
strict_fma.f64.ll
[FPEnv][AMDGPU] Correct strictfp tests.
2023-07-25 13:24:46 -04:00
sub.v2i16.ll
AMDGPU: Fix packed 16-bit inline constants (#76522)
2024-01-04 00:10:15 +01:00
subo.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc.ll
…
twoaddr-extract-dyn-v7f64.mir
[TwoAddressInstruction] Propagate undef flags for partial defs (#79286)
2024-02-07 16:46:00 +09:00
uaddsat.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
ubfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
udiv.i32.ll
[AMDGPU] Use correct number of bits needed for div/rem shrinking (#80622)
2024-02-06 21:32:28 +05:30
udiv.i64.ll
[GlobalIsel] Combine ADDO (#82927)
2024-03-14 12:45:19 +01:00
udivrem.ll
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171)
2024-03-08 09:39:10 +01:00
umed3.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
unsupported-load.ll
…
unsupported-ptr-add.ll
…
urem.i32.ll
[AMDGPU] Use correct number of bits needed for div/rem shrinking (#80622)
2024-02-06 21:32:28 +05:30
urem.i64.ll
[GlobalIsel] Combine ADDO (#82927)
2024-03-14 12:45:19 +01:00
usubsat.ll
[AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710)
2023-11-13 13:53:10 +00:00
v_bfe_i32.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
widen-i8-i16-scalar-loads.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w32-imm.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w32-iu-modifiers.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w32-swmmac-index_key.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w32.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w64-imm.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w64-iu-modifiers.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w64-swmmac-index_key.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
wmma-gfx12-w64.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
xnor.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
zextload.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00