9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
107 lines
2.4 KiB
YAML
107 lines
2.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: ptrtoint_s_p3_to_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: ptrtoint_s_p3_to_s_s32
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; CHECK: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(p3) = COPY $sgpr0
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%1:sgpr(s32) = G_PTRTOINT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: ptrtoint_s_p5_to_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: ptrtoint_s_p5_to_s_s32
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; CHECK: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(p5) = COPY $sgpr0
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%1:sgpr(s32) = G_PTRTOINT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: ptrtoint_s_p0_to_s_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: ptrtoint_s_p0_to_s_s64
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(p0) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_PTRTOINT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: ptrtoint_s_p1_to_s_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: ptrtoint_s_p1_to_s_s64
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(p1) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_PTRTOINT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: ptrtoint_s_p999_to_s_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: ptrtoint_s_p999_to_s_s64
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(p999) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_PTRTOINT %0
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S_ENDPGM 0, implicit %1
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...
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