3cf539fb04
Call generateWaitcnt unconditionally at the end of SIInsertWaitcnts::insertWaitcntInBlock. Even if we don't need to generate a new waitcnt instruction it has the effect of combining or removing redundant waitcnts that were already present. Tests show various small improvements in waitcnt placement.
153 lines
5.6 KiB
LLVM
153 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s
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; TODO: Merge with DAG test
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define amdgpu_kernel void @is_local_vgpr(ptr addrspace(1) %ptr.ptr) {
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; CI-LABEL: is_local_vgpr:
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; CI: ; %bb.0:
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; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; CI-NEXT: s_load_dword s2, s[4:5], 0x33
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; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; CI-NEXT: s_waitcnt lgkmcnt(0)
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; CI-NEXT: v_mov_b32_e32 v0, s0
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; CI-NEXT: v_mov_b32_e32 v1, s1
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; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v2
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; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
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; CI-NEXT: s_waitcnt vmcnt(0)
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; CI-NEXT: v_cmp_eq_u32_e32 vcc, s2, v1
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; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; CI-NEXT: flat_store_dword v[0:1], v0
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; CI-NEXT: s_endpgm
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;
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; GFX9-LABEL: is_local_vgpr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_mov_b64 s[0:1], src_shared_base
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; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s1, v1
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; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: is_local_vgpr:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: s_waitcnt_depctr 0xffe3
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; GFX10-NEXT: s_mov_b64 s[0:1], src_shared_base
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; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v1
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; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; GFX10-NEXT: global_store_dword v[0:1], v0, off
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: is_local_vgpr:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] glc dlc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: s_mov_b64 s[0:1], src_shared_base
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v1
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; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; GFX11-NEXT: global_store_b32 v[0:1], v0, off
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds ptr, ptr addrspace(1) %ptr.ptr, i32 %id
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%ptr = load volatile ptr, ptr addrspace(1) %gep
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%val = call i1 @llvm.amdgcn.is.shared(ptr %ptr)
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%ext = zext i1 %val to i32
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store i32 %ext, ptr addrspace(1) undef
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ret void
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}
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define amdgpu_kernel void @is_local_sgpr(ptr %ptr) {
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; CI-LABEL: is_local_sgpr:
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; CI: ; %bb.0:
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; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; CI-NEXT: s_waitcnt lgkmcnt(0)
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; CI-NEXT: s_load_dword s0, s[4:5], 0x33
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; CI-NEXT: s_waitcnt lgkmcnt(0)
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; CI-NEXT: s_cmp_lg_u32 s1, s0
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; CI-NEXT: s_cbranch_scc1 .LBB1_2
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; CI-NEXT: ; %bb.1: ; %bb0
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; CI-NEXT: v_mov_b32_e32 v0, 0
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; CI-NEXT: flat_store_dword v[0:1], v0
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; CI-NEXT: s_waitcnt vmcnt(0)
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; CI-NEXT: .LBB1_2: ; %bb1
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; CI-NEXT: s_endpgm
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;
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; GFX9-LABEL: is_local_sgpr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX9-NEXT: s_mov_b64 s[2:3], src_shared_base
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_cmp_lg_u32 s1, s3
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; GFX9-NEXT: s_cbranch_scc1 .LBB1_2
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; GFX9-NEXT: ; %bb.1: ; %bb0
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: global_store_dword v[0:1], v0, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: .LBB1_2: ; %bb1
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: is_local_sgpr:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX10-NEXT: s_mov_b64 s[2:3], src_shared_base
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_cmp_lg_u32 s1, s3
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; GFX10-NEXT: s_cbranch_scc1 .LBB1_2
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; GFX10-NEXT: ; %bb.1: ; %bb0
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: global_store_dword v[0:1], v0, off
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: .LBB1_2: ; %bb1
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: is_local_sgpr:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
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; GFX11-NEXT: s_mov_b64 s[2:3], src_shared_base
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_cmp_lg_u32 s1, s3
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; GFX11-NEXT: s_cbranch_scc1 .LBB1_2
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; GFX11-NEXT: ; %bb.1: ; %bb0
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; GFX11-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: .LBB1_2: ; %bb1
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; GFX11-NEXT: s_endpgm
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%val = call i1 @llvm.amdgcn.is.shared(ptr %ptr)
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br i1 %val, label %bb0, label %bb1
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bb0:
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store volatile i32 0, ptr addrspace(1) undef
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br label %bb1
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bb1:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i1 @llvm.amdgcn.is.shared(ptr nocapture) #0
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attributes #0 = { nounwind readnone speculatable }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
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