f2c164c815
SIInsertWaitcnts inserts waitcnt instructions to resolve data dependencies. The GFX10+ vscnt (VMEM store count) counter is never used in this way. It is only used to resolve memory dependencies, and that is handled by SIMemoryLegalizer. Hence there is no need to conservatively wait for vscnt to be 0 on function entry and before returns. Differential Revision: https://reviews.llvm.org/D153537
132 lines
3.8 KiB
LLVM
132 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefixes=GCN %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefixes=GCN %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefixes=GCN %s
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; Test vector signed bitfield extract.
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define signext i8 @v_ashr_i8_i32(i32 %value) {
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; GCN-LABEL: v_ashr_i8_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_bfe_i32 v0, v0, 4, 8
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%1 = ashr i32 %value, 4
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%2 = trunc i32 %1 to i8
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ret i8 %2
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}
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define signext i16 @v_ashr_i16_i32(i32 %value) {
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; GCN-LABEL: v_ashr_i16_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_bfe_i32 v0, v0, 9, 16
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%1 = ashr i32 %value, 9
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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define signext i8 @v_lshr_i8_i32(i32 %value) {
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; GCN-LABEL: v_lshr_i8_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_bfe_i32 v0, v0, 4, 8
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%1 = lshr i32 %value, 4
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%2 = trunc i32 %1 to i8
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ret i8 %2
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}
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define signext i16 @v_lshr_i16_i32(i32 %value) {
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; GCN-LABEL: v_lshr_i16_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_bfe_i32 v0, v0, 9, 16
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%1 = lshr i32 %value, 9
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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; Test vector bitfield extract for 64-bits.
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define i64 @v_ashr_i64(i64 %value) {
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; GCN-LABEL: v_ashr_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 4
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%1 = ashr i64 %value, 10
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%2 = shl i64 %1, 60
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%3 = ashr i64 %2, 60
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ret i64 %3
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}
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define i64 @v_lshr_i64(i64 %value) {
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; GCN-LABEL: v_lshr_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 4
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%1 = lshr i64 %value, 10
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%2 = shl i64 %1, 60
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%3 = ashr i64 %2, 60
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ret i64 %3
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}
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; Test scalar signed bitfield extract.
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define amdgpu_ps signext i8 @s_ashr_i8_i32(i32 inreg %value) {
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; GCN-LABEL: s_ashr_i8_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_i32 s0, s0, 0x80004
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; GCN-NEXT: ; return to shader part epilog
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%1 = ashr i32 %value, 4
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%2 = trunc i32 %1 to i8
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ret i8 %2
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}
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define amdgpu_ps signext i16 @s_ashr_i16_i32(i32 inreg %value) {
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; GCN-LABEL: s_ashr_i16_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_i32 s0, s0, 0x100009
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; GCN-NEXT: ; return to shader part epilog
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%1 = ashr i32 %value, 9
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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define amdgpu_ps signext i8 @s_lshr_i8_i32(i32 inreg %value) {
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; GCN-LABEL: s_lshr_i8_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_i32 s0, s0, 0x80004
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; GCN-NEXT: ; return to shader part epilog
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%1 = lshr i32 %value, 4
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%2 = trunc i32 %1 to i8
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ret i8 %2
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}
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define amdgpu_ps signext i16 @s_lshr_i16_i32(i32 inreg %value) {
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; GCN-LABEL: s_lshr_i16_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_i32 s0, s0, 0x100009
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; GCN-NEXT: ; return to shader part epilog
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%1 = lshr i32 %value, 9
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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; Test scalar bitfield extract for 64-bits.
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define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value) {
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; GCN-LABEL: s_ashr_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x40001
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; GCN-NEXT: ; return to shader part epilog
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%1 = ashr i64 %value, 1
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%2 = shl i64 %1, 60
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%3 = ashr i64 %2, 60
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ret i64 %3
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}
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