9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
296 lines
7.4 KiB
YAML
296 lines
7.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
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---
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name: anyext_sgpr_s16_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: $sgpr0 = COPY [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s32) = G_ANYEXT %1
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$sgpr0 = COPY %2
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...
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---
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name: anyext_sgpr_s32_to_sgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s64) = G_ANYEXT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: anyext_sgpr_s16_to_sgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s64) = G_ANYEXT %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: anyext_vgpr_s32_to_vgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s64) = G_ANYEXT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: anyext_vgpr_s16_to_vgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s64) = G_ANYEXT %1
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S_ENDPGM 0, implicit %2
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...
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# vcc is an invalid extension source
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# ---
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# name: anyext_vcc_s1_to_vgpr_s32
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# legalized: true
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# regBankSelected: true
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# body: |
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# bb.0:
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# liveins: $vgpr0
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# %0:vgpr(s32) = COPY $vgpr0
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# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
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# %2:vgpr(s32) = G_ANYEXT %1
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# $vgpr0 = COPY %2
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# ...
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---
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name: anyext_sgpr_s1_to_sgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s16
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
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; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc
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; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s16) = G_ANYEXT %1
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%3:sgpr(s32) = G_ZEXT %2
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$sgpr0 = COPY %3
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...
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---
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name: anyext_sgpr_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: $sgpr0 = COPY [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s32) = G_ANYEXT %1
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$sgpr0 = COPY %2
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...
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---
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name: anyext_sgpr_s1_to_sgpr_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s64) = G_ANYEXT %1
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$sgpr0_sgpr1 = COPY %2
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...
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---
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name: anyext_vgpr_s1_to_vgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
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; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s16) = G_ANYEXT %1
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%3:vgpr(s32) = G_ZEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: anyext_vgpr_s1_to_vgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: $vgpr0 = COPY [[COPY]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s32) = G_ANYEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: anyext_sgpr_s1_to_vgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: $sgpr0 = COPY [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s32) = G_ANYEXT %1
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$sgpr0 = COPY %2
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...
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---
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name: anyext_vgpr_s16_to_vgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: $vgpr0 = COPY [[COPY]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s32) = G_ANYEXT %1
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$vgpr0 = COPY %2
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...
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# The source register already has an assigned register class that
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# should not be interpreted as vcc.
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---
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name: anyext_regclass_sgpr_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: $sgpr0 = COPY [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sreg_32(s1) = G_TRUNC %0
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%2:sgpr(s32) = G_ANYEXT %1
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$sgpr0 = COPY %2
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...
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