9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
117 lines
3.8 KiB
YAML
117 lines
3.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
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---
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name: smax_neg_abs_pattern_s32_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss
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; GFX6: liveins: $sgpr0
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0
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; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
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; GFX6-NEXT: S_ENDPGM 0, implicit %smax
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;
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; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss
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; GFX9: liveins: $sgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
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; GFX9-NEXT: S_ENDPGM 0, implicit %smax
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%src0:sgpr(s32) = COPY $sgpr0
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%zero:sgpr(s32) = G_CONSTANT i32 0
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%ineg:sgpr(s32) = G_SUB %zero, %src0
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%smax:sgpr(s32) = G_SMAX %src0, %ineg
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S_ENDPGM 0, implicit %smax
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...
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---
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name: smax_neg_abs_pattern_s32_ss_commute
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
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; GFX6: liveins: $sgpr0
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0
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; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
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; GFX6-NEXT: S_ENDPGM 0, implicit %smax
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;
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; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
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; GFX9: liveins: $sgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0
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; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
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; GFX9-NEXT: S_ENDPGM 0, implicit %smax
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%src0:sgpr(s32) = COPY $sgpr0
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%zero:sgpr(s32) = G_CONSTANT i32 0
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%ineg:sgpr(s32) = G_SUB %zero, %src0
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%smax:sgpr(s32) = G_SMAX %ineg, %src0
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S_ENDPGM 0, implicit %smax
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...
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---
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name: smax_neg_abs_pattern_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX6-LABEL: name: smax_neg_abs_pattern_s32_vv
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; GFX6: liveins: $vgpr0
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; GFX6-NEXT: {{ $}}
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; GFX6-NEXT: %src0:vgpr_32 = COPY $vgpr0
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; GFX6-NEXT: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX6-NEXT: %ineg:vgpr_32, dead %4:sreg_64 = V_SUB_CO_U32_e64 %zero, %src0, 0, implicit $exec
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; GFX6-NEXT: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
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; GFX6-NEXT: S_ENDPGM 0, implicit %smax
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;
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; GFX9-LABEL: name: smax_neg_abs_pattern_s32_vv
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; GFX9: liveins: $vgpr0
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; GFX9-NEXT: {{ $}}
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; GFX9-NEXT: %src0:vgpr_32 = COPY $vgpr0
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; GFX9-NEXT: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX9-NEXT: %ineg:vgpr_32 = V_SUB_U32_e64 %zero, %src0, 0, implicit $exec
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; GFX9-NEXT: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
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; GFX9-NEXT: S_ENDPGM 0, implicit %smax
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%src0:vgpr(s32) = COPY $vgpr0
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%zero:vgpr(s32) = G_CONSTANT i32 0
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%ineg:vgpr(s32) = G_SUB %zero, %src0
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%smax:vgpr(s32) = G_SMAX %src0, %ineg
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S_ENDPGM 0, implicit %smax
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...
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# FIXME: Violates constant bus restriction
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# ---
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# name: smax_neg_abs_pattern_s32_vs
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# legalized: true
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# regBankSelected: true
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# body: |
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# bb.0:
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# liveins: $sgpr0
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# %src0:sgpr(s32) = COPY $sgpr0
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# %zero:sgpr(s32) = G_CONSTANT i32 0
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# %ineg:sgpr(s32) = G_SUB %zero, %src0
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# %smax:vgpr(s32) = G_SMAX %src0, %ineg
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# S_ENDPGM 0, implicit %smax
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# ...
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