9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
211 lines
6.2 KiB
LLVM
211 lines
6.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX90A %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX908 %s
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; GCN-LABEL: {{^}}func_empty:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_empty() #0 {
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_4:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: use agpr3
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_areg_4() #0 {
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call void asm sideeffect "; use agpr3", "~{a3}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_32:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: use agpr31
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_areg_32() #0 {
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call void asm sideeffect "; use agpr31", "~{a31}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_33:
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; GCN-NOT: a32
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; GFX90A: v_accvgpr_read_b32 v0, a32 ; Reload Reuse
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; GCN-NOT: a32
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; GCN: use agpr32
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; GCN-NOT: a32
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; GFX90A: v_accvgpr_write_b32 a32, v0 ; Reload Reuse
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; GCN-NOT: a32
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; GCN: s_setpc_b64
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define void @func_areg_33() #0 {
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call void asm sideeffect "; use agpr32", "~{a32}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_64:
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; GFX908-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX90A: v_accvgpr_read_b32 v0, a63 ; Reload Reuse
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; GCN: use agpr63
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; GFX90A: v_accvgpr_write_b32 a63, v0 ; Reload Reuse
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_areg_64() #0 {
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call void asm sideeffect "; use agpr63", "~{a63}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_31_63:
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; GFX908-NOT: buffer_
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; GFX908-NOT: v_accvgpr
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; GFX908-NOT: buffer
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; GFX90A: v_accvgpr_read_b32 v0, a63 ; Reload Reuse
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; GCN: use agpr31, agpr63
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; GFX90A: v_accvgpr_write_b32 a63, v0 ; Reload Reuse
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; GFX908-NOT: v_accvgpr
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; GFX908-NOT: buffer
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; GCN: s_setpc_b64
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define void @func_areg_31_63() #0 {
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call void asm sideeffect "; use agpr31, agpr63", "~{a31},~{a63}" ()
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ret void
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}
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declare void @func_unknown() #0
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; GCN-LABEL: {{^}}test_call_empty:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: def a[0:31]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_empty() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_empty()
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store volatile <32 x float> %reg, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg4:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[4:35]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg4() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_4()
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store volatile <32 x float> %reg, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg32:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[32:63]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg32() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_32()
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store volatile <32 x float> %reg, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg64:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: def a[0:31]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg64() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_64()
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store volatile <32 x float> %reg, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg31_63:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[32:63]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg31_63() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_31_63()
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store volatile <32 x float> %reg, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_unknown:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[32:63]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_unknown() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_unknown()
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store volatile <32 x float> %reg, ptr addrspace(1) undef
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ret void
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}
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attributes #0 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" }
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