9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
54 lines
2.3 KiB
LLVM
54 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: name: s_ctpop_i32
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; GCN: S_BCNT1_I32_B32
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define amdgpu_kernel void @s_ctpop_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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store i32 %ctpop, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: s_ctpop_i64
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; GCN: %[[BCNT:[0-9]+]]:sreg_32 = S_BCNT1_I32_B64
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; GCN: %[[SREG1:[0-9]+]]:sreg_32 = COPY %[[BCNT]]
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; GCN: %[[SREG2:[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: REG_SEQUENCE killed %[[SREG1]], %subreg.sub0, killed %[[SREG2]], %subreg.sub1
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define amdgpu_kernel void @s_ctpop_i64(ptr addrspace(1) noalias %out, i64 %val) nounwind {
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%truncctpop = trunc i64 %ctpop to i32
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store i32 %truncctpop, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_ctpop_i32
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; GCN: V_BCNT_U32_B32_e64
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define amdgpu_kernel void @v_ctpop_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid
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%val = load i32, ptr addrspace(1) %in.gep, align 4
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%ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
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store i32 %ctpop, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_ctpop_i64
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; GCN: %[[BCNT1:[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 killed %{{[0-9]+}}, 0, implicit $exec
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; GCN: %[[BCNT2:[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 killed %{{[0-9]+}}, killed %[[BCNT1]], implicit $exec
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; GCN: %[[VGPR1:[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GCN: REG_SEQUENCE killed %[[BCNT2]], %subreg.sub0, killed %[[VGPR1]], %subreg.sub1
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define amdgpu_kernel void @v_ctpop_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
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%val = load i64, ptr addrspace(1) %in.gep, align 8
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%truncctpop = trunc i64 %ctpop to i32
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store i32 %truncctpop, ptr addrspace(1) %out, align 4
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ret void
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}
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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