9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
78 lines
4.0 KiB
LLVM
78 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A
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; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS
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; GCN-LABEL: {{^}}dpp64_ceil:
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; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]],
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; DPP64: v_ceil_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp64_ceil(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%round = tail call double @llvm.ceil.f64(double %tmp1)
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%tmp2 = bitcast double %round to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_rcp:
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; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]],
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; DPP64: v_rcp_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp64_rcp(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = call double @llvm.amdgcn.rcp.f64(double %tmp1)
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_rcp_unsupported_ctl:
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; GCN-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GCN: v_rcp_f64_e32
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define amdgpu_kernel void @dpp64_rcp_unsupported_ctl(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = fdiv fast double 1.0, %tmp1
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_div:
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; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]],
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; DPPMOV64: v_mov_b64_dpp v[{{[0-9:]+}}], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GFX90A-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GFX10PLUS-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GCN: v_div_scale_f64
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; GCN: v_rcp_f64_e32
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define amdgpu_kernel void @dpp64_div(ptr addrspace(1) %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
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%load = load i64, ptr addrspace(1) %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = fdiv double 15.0, %tmp1
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, ptr addrspace(1) %gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32, i32, i32, i1) #0
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declare double @llvm.ceil.f64(double)
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declare double @llvm.amdgcn.rcp.f64(double)
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attributes #0 = { nounwind readnone convergent }
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