9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
78 lines
3.3 KiB
YAML
78 lines
3.3 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: flat_load_clustering
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# GCN: FLAT_LOAD_DWORD
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# GCN-NEXT: FLAT_LOAD_DWORD
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--- |
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define amdgpu_kernel void @flat_load_clustering(ptr addrspace(1) nocapture %arg, ptr addrspace(4) nocapture readonly %arg1) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%idxprom = sext i32 %tid to i64
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%gep1 = getelementptr inbounds i32, ptr addrspace(4) %arg1, i64 %idxprom
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%load1 = load i32, ptr addrspace(4) %gep1, align 4
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%gep2 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %idxprom
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%gep34 = getelementptr inbounds i32, ptr addrspace(4) %gep1, i64 4
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%load2 = load i32, ptr addrspace(4) %gep34, align 4
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%gep4 = getelementptr inbounds i32, ptr addrspace(1) %gep2, i64 4
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store i32 %load1, ptr addrspace(1) %gep2, align 4
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store i32 %load2, ptr addrspace(1) %gep4, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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...
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---
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name: flat_load_clustering
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: sgpr_64 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: vgpr_32 }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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- { id: 8, class: vgpr_32 }
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- { id: 9, class: vreg_64 }
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- { id: 10, class: vreg_64 }
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- { id: 11, class: vgpr_32 }
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- { id: 12, class: vreg_64 }
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- { id: 13, class: vreg_64 }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr4_sgpr5', virtual-reg: '%1' }
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body: |
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bb.0.bb:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1 = COPY $sgpr4_sgpr5
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%0 = COPY $vgpr0
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%3 = S_LOAD_DWORDX2_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
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%4 = S_LOAD_DWORDX2_IMM %1, 8, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
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%7 = V_LSHLREV_B32_e32 2, %0, implicit $exec
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%2 = V_MOV_B32_e32 0, implicit $exec
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undef %12.sub0 = V_ADD_CO_U32_e32 %4.sub0, %7, implicit-def $vcc, implicit $exec
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%11 = COPY %4.sub1
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%12.sub1 = V_ADDC_U32_e32 %11, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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%5 = FLAT_LOAD_DWORD %12, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.gep1)
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undef %9.sub0 = V_ADD_CO_U32_e32 %3.sub0, %7, implicit-def $vcc, implicit $exec
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%8 = COPY %3.sub1
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%9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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undef %13.sub0 = V_ADD_CO_U32_e32 16, %12.sub0, implicit-def $vcc, implicit $exec
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%13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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%6 = FLAT_LOAD_DWORD %13, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.gep34)
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undef %10.sub0 = V_ADD_CO_U32_e32 16, %9.sub0, implicit-def $vcc, implicit $exec
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%10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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FLAT_STORE_DWORD %9, %5, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.gep2)
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FLAT_STORE_DWORD %10, %6, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.gep4)
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S_ENDPGM 0
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...
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