9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
89 lines
2.9 KiB
YAML
89 lines
2.9 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx902 -mattr=+xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK,GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64,-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s
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# GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr_hidden_bundle
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# GCN: bb.0:
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# GCN: }
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# XNACK-NEXT: S_NOP
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# NOXNACK-NOT: S_NOP
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# GCN: S_LOAD_DWORDX2_IMM
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---
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name: break_smem_clause_simple_load_smrd8_ptr_hidden_bundle
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body: |
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bb.0:
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BUNDLE implicit-def $sgpr6_sgpr7 {
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$sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0
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}
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$sgpr14_sgpr15 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
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S_ENDPGM 0
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...
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# GFX9-LABEL: name: hazard_precedes_bundle
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# GFX9: S_MOV_B32
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# GFX9-NEXT: S_NOP
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# GFX9: BUNDLE
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# GFX9-NEXT: S_NOP
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---
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name: hazard_precedes_bundle
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body: |
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bb.0:
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$m0 = S_MOV_B32 $sgpr7
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S_SENDMSG 3, implicit $exec, implicit $m0
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$m0 = S_MOV_B32 $sgpr8
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BUNDLE implicit-def $vgpr0 {
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$vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
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}
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S_ENDPGM 0
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...
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# GCN-LABEL: name: vmem_vcc_hazard_ignore_bundle_instr
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# GCN: S_LOAD_DWORDX2_IMM
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# GCN-NEXT: }
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# GFX9-NEXT: S_NOP 3
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_hazard_ignore_bundle_instr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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BUNDLE implicit-def $vgpr1, implicit $vgpr0, implicit $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec {
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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}
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BUNDLE implicit-def $sgpr0_sgpr1, implicit $sgpr10_sgpr11 {
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$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0
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}
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two_after_bundle
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# GCN: bb.2:
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# GFX9-NEXT: S_NOP 4
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two_after_bundle
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body: |
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bb.0:
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successors: %bb.2
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BUNDLE implicit-def $vgpr1, implicit $vgpr0 {
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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}
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S_NOP 0
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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BUNDLE implicit-def $vgpr1, implicit $vgpr0 {
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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}
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bb.2:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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...
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