faa2c678aa
In order to enable the LLVM frontend to better analyze buffer operations (and to potentially enable more precise analyses on the backend), define versions of the raw and structured buffer intrinsics that use `ptr addrspace(8)` instead of `<4 x i32>` to represent their rsrc arguments. The new intrinsics are named by replacing `buffer.` with `buffer.ptr`. One advantage to these intrinsic definitions is that, instead of specifying that a buffer load/store will read/write some memory, we can indicate that the memory read or written will be based on the pointer argument. This means that, for example, a read from a `noalias` buffer can be pulled out of a loop that is modifying a distinct buffer. In the future, we will define custom PseudoSourceValues that will allow us to package up the (buffer, index, offset) triples that buffer intrinsics contain and allow for more precise backend analysis. This work also enables creating address space 7, which represents manipulation of raw buffers using native LLVM load and store instructions. Where tests simply used a buffer intrinsic while testing some other code path (such as the tests for VGPR spills), they have been updated to use the new intrinsic form. Tests that are "about" buffer intrinsics (for instance, those that ensure that they codegen as expected) have been duplicated, either within existing files or into new ones. Depends on D145441 Reviewed By: arsenm, #amdgpu Differential Revision: https://reviews.llvm.org/D147547
88 lines
3.1 KiB
LLVM
88 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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define amdgpu_ps void @i1_copy_from_loop(ptr addrspace(8) inreg %rsrc, i32 %tid) {
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; SI-LABEL: i1_copy_from_loop:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_mov_b32 s14, 0
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; SI-NEXT: s_mov_b64 s[4:5], 0
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; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
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; SI-NEXT: ; implicit-def: $sgpr8_sgpr9
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; SI-NEXT: s_branch .LBB0_3
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; SI-NEXT: .LBB0_1: ; in Loop: Header=BB0_3 Depth=1
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; SI-NEXT: ; implicit-def: $sgpr14
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; SI-NEXT: .LBB0_2: ; %Flow
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; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; SI-NEXT: s_and_b64 s[12:13], exec, s[8:9]
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; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5]
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; SI-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
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; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec
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; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
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; SI-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; SI-NEXT: s_cbranch_execz .LBB0_7
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; SI-NEXT: .LBB0_3: ; %for.body
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_cmp_lt_u32 s14, 4
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; SI-NEXT: s_cselect_b64 s[10:11], -1, 0
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; SI-NEXT: s_or_b64 s[8:9], s[8:9], exec
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; SI-NEXT: s_cmp_gt_u32 s14, 3
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; SI-NEXT: s_cbranch_scc1 .LBB0_1
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; SI-NEXT: ; %bb.4: ; %mid.loop
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; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; SI-NEXT: v_mov_b32_e32 v1, s14
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; SI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 idxen offen
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; SI-NEXT: s_mov_b64 s[10:11], -1
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cmp_le_f32_e32 vcc, 0, v1
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; SI-NEXT: s_mov_b64 s[8:9], -1
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; SI-NEXT: s_and_saveexec_b64 s[12:13], vcc
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; SI-NEXT: ; %bb.5: ; %end.loop
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; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; SI-NEXT: s_add_i32 s14, s14, 1
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; SI-NEXT: s_xor_b64 s[8:9], exec, -1
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; SI-NEXT: ; %bb.6: ; %Flow1
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; SI-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; SI-NEXT: s_or_b64 exec, exec, s[12:13]
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; SI-NEXT: s_branch .LBB0_2
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; SI-NEXT: .LBB0_7: ; %for.end
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; SI-NEXT: s_or_b64 exec, exec, s[4:5]
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; SI-NEXT: s_and_saveexec_b64 s[0:1], s[6:7]
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; SI-NEXT: s_cbranch_execz .LBB0_9
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; SI-NEXT: ; %bb.8: ; %if
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; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm
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; SI-NEXT: .LBB0_9: ; %end
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; SI-NEXT: s_endpgm
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entry:
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br label %for.body
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for.body:
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%i = phi i32 [0, %entry], [%i.inc, %end.loop]
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%cc = icmp ult i32 %i, 4
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br i1 %cc, label %mid.loop, label %for.end
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mid.loop:
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%v = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %tid, i32 %i, i32 0, i32 0)
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%cc2 = fcmp oge float %v, 0.0
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br i1 %cc2, label %end.loop, label %for.end
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end.loop:
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%i.inc = add i32 %i, 1
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br label %for.body
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for.end:
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br i1 %cc, label %if, label %end
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if:
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true)
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br label %end
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end:
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ret void
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}
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declare float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32, i32 immarg) #0
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
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attributes #0 = { nounwind memory(argmem: read) }
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attributes #1 = { nounwind inaccessiblememonly }
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