9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
183 lines
7.4 KiB
LLVM
183 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-GISEL %s
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define amdgpu_kernel void @test_get_doorbell(ptr addrspace(1) %out) {
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; GFX11-SDAG-LABEL: test_get_doorbell:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DOORBELL)
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-SDAG-NEXT: s_nop 0
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; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: test_get_doorbell:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DOORBELL)
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_nop 0
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; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-GISEL-NEXT: s_endpgm
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%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 128)
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store i32 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_get_ddid(ptr addrspace(1) %out) {
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; GFX11-SDAG-LABEL: test_get_ddid:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DDID)
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-SDAG-NEXT: s_nop 0
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; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: test_get_ddid:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DDID)
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_nop 0
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; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-GISEL-NEXT: s_endpgm
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%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 129)
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store i32 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_get_tma(ptr addrspace(1) %out) {
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; GFX11-LABEL: test_get_tma:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TMA)
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 130)
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store i64 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_get_realtime(ptr addrspace(1) %out) {
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; GFX11-LABEL: test_get_realtime:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 131)
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store i64 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_savewave(ptr addrspace(1) %out) {
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; GFX11-SDAG-LABEL: test_savewave:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_SAVE_WAVE)
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-SDAG-NEXT: s_nop 0
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; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: test_savewave:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_SAVE_WAVE)
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_nop 0
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; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-GISEL-NEXT: s_endpgm
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%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 132)
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store i32 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_get_tba(ptr addrspace(1) %out) {
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; GFX11-LABEL: test_get_tba:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TBA)
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 133)
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store i64 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_get_0_i32(ptr addrspace(1) %out) {
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; GFX11-SDAG-LABEL: test_get_0_i32:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(0, 0, 0)
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; GFX11-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-SDAG-NEXT: s_nop 0
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; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: test_get_0_i32:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(0, 0, 0)
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_nop 0
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; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-GISEL-NEXT: s_endpgm
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%ret = call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 0)
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store i32 %ret, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_get_99999_i64(ptr addrspace(1) %out) {
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; GFX11-LABEL: test_get_99999_i64:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], 99999
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%ret = call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 99999)
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store i64 %ret, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32)
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declare i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32)
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