9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
226 lines
7.9 KiB
LLVM
226 lines
7.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SICIVI %s
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; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,SICIVI,CIPLUS %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SICIVI,CIPLUS %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,CIPLUS %s
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; GCN-LABEL: {{^}}local_i32_load
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28
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; GCN: buffer_store_dword [[REG]],
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define amdgpu_kernel void @local_i32_load(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%gep = getelementptr i32, ptr addrspace(3) %in, i32 7
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%val = load i32, ptr addrspace(3) %gep, align 4
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i32_load_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}}
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; GCN: buffer_store_dword [[REG]],
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define amdgpu_kernel void @local_i32_load_0_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%val = load i32, ptr addrspace(3) %in, align 4
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store i32 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i8_load_i16_max_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535
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; GCN: buffer_store_byte [[REG]],
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define amdgpu_kernel void @local_i8_load_i16_max_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%gep = getelementptr i8, ptr addrspace(3) %in, i32 65535
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%val = load i8, ptr addrspace(3) %gep, align 4
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store i8 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i8_load_over_i16_max_offset:
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; SICIVI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
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; SI, which is why it is being OR'd with the base pointer.
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; SI-DAG: s_bitset1_b32 [[ADDR:s[0-9]+]], 16
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; CI-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; VI-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; GFX9-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; GCN-DAG: v_mov_b32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
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; GCN: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]]
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; GCN: buffer_store_byte [[REG]],
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define amdgpu_kernel void @local_i8_load_over_i16_max_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%gep = getelementptr i8, ptr addrspace(3) %in, i32 65536
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%val = load i8, ptr addrspace(3) %gep, align 4
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store i8 %val, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_load:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_i64_load(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%gep = getelementptr i64, ptr addrspace(3) %in, i32 7
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%val = load i64, ptr addrspace(3) %gep, align 8
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store i64 %val, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_load_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_i64_load_0_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%val = load i64, ptr addrspace(3) %in, align 8
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store i64 %val, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_load:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_f64_load(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%gep = getelementptr double, ptr addrspace(3) %in, i32 7
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%val = load double, ptr addrspace(3) %gep, align 8
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store double %val, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_load_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
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; GCN: buffer_store_dwordx2 [[REG]],
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define amdgpu_kernel void @local_f64_load_0_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) nounwind {
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%val = load double, ptr addrspace(3) %in, align 8
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store double %val, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
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define amdgpu_kernel void @local_i64_store(ptr addrspace(3) %out) nounwind {
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%gep = getelementptr i64, ptr addrspace(3) %out, i32 7
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store i64 5678, ptr addrspace(3) %gep, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_i64_store_0_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @local_i64_store_0_offset(ptr addrspace(3) %out) nounwind {
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store i64 1234, ptr addrspace(3) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
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define amdgpu_kernel void @local_f64_store(ptr addrspace(3) %out) nounwind {
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%gep = getelementptr double, ptr addrspace(3) %out, i32 7
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store double 16.0, ptr addrspace(3) %gep, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_f64_store_0_offset
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @local_f64_store_0_offset(ptr addrspace(3) %out) nounwind {
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store double 20.0, ptr addrspace(3) %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_v2i64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; SI: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:14 offset1:15
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; CIPLUS: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v2i64_store(ptr addrspace(3) %out) nounwind {
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%gep = getelementptr <2 x i64>, ptr addrspace(3) %out, i32 7
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store <2 x i64> <i64 5678, i64 5678>, ptr addrspace(3) %gep, align 16
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ret void
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}
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; GCN-LABEL: {{^}}local_v2i64_store_0_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; SI: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:1{{$}}
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; CIPLUS: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v2i64_store_0_offset(ptr addrspace(3) %out) nounwind {
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store <2 x i64> <i64 1234, i64 1234>, ptr addrspace(3) %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}local_v4i64_store:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:30 offset1:31
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; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:28 offset1:29
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; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224{{$}}
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; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240{{$}}
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v4i64_store(ptr addrspace(3) %out) nounwind {
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%gep = getelementptr <4 x i64>, ptr addrspace(3) %out, i32 7
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store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, ptr addrspace(3) %gep, align 16
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ret void
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}
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; GCN-LABEL: {{^}}local_v4i64_store_0_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-NOT: add
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; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:2 offset1:3
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; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:1
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; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
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; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16{{$}}
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; GCN: s_endpgm
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define amdgpu_kernel void @local_v4i64_store_0_offset(ptr addrspace(3) %out) nounwind {
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store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, ptr addrspace(3) %out, align 16
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ret void
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}
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