9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
36 lines
1.5 KiB
LLVM
36 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; This is used to crash in LiveIntervalAnalysis via SILoadStoreOptimizer
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; while fixing up the merge of two ds_write instructions.
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@tess_lds = external addrspace(3) global [8192 x i32]
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; CHECK-LABEL: {{^}}main:
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; CHECK-DAG: ds_write_b32
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; CHECK-DAG: ds_write_b32
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; CHECK-DAG: v_mov_b32_e32 v1, v0
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; CHECK: tbuffer_store_format_xyzw v[0:3],
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define amdgpu_vs void @main(i32 inreg %arg) {
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main_body:
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%tmp = load float, ptr addrspace(3) undef, align 4
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%tmp1 = load float, ptr addrspace(3) undef, align 4
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store float %tmp, ptr addrspace(3) null, align 4
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%tmp2 = bitcast float %tmp to i32
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%tmp3 = add nuw nsw i32 0, 1
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = getelementptr [8192 x i32], ptr addrspace(3) @tess_lds, i64 0, i64 %tmp4
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store float %tmp1, ptr addrspace(3) %tmp5, align 4
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%tmp7 = bitcast float %tmp1 to i32
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%tmp8 = insertelement <4 x i32> undef, i32 %tmp2, i32 0
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%tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp7, i32 1
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%tmp10 = insertelement <4 x i32> %tmp9, i32 undef, i32 2
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%tmp11 = insertelement <4 x i32> %tmp10, i32 undef, i32 3
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call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %tmp11, ptr addrspace(8) undef, i32 0, i32 0, i32 %arg, i32 78, i32 3) #2
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ret void
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}
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declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32>, ptr addrspace(8), i32, i32, i32, i32 immarg, i32 immarg) #0
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attributes #0 = { nounwind willreturn writeonly }
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