9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
27 lines
922 B
LLVM
27 lines
922 B
LLVM
;RUN: llc < %s -mtriple=r600 -mcpu=cayman
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; CHECK-LABEL: {{^}}main:
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; CHECK: PRED_SETE_INT * Pred,
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; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one
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define amdgpu_ps void @main(<4 x float> inreg) {
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main_body:
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%1 = extractelement <4 x float> %0, i32 0
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%2 = bitcast float %1 to i32
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%3 = icmp eq i32 %2, 0
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br i1 %3, label %IF, label %ENDIF
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IF: ; preds = %main_body
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%4 = call float @llvm.r600.dot4(<4 x float> %0, <4 x float> %0)
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br label %ENDIF
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ENDIF: ; preds = %IF, %main_body
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%5 = phi float [%4, %IF], [0.000000e+00, %main_body]
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%6 = insertelement <4 x float> undef, float %5, i32 0
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call void @llvm.r600.store.swizzle(<4 x float> %6, i32 0, i32 0)
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ret void
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}
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declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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attributes #1 = { readnone }
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