9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
105 lines
3.6 KiB
LLVM
105 lines
3.6 KiB
LLVM
; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
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; OPT-LABEL: @annotate_unreachable_noloop(
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; OPT-NOT: call i1 @llvm.amdgcn.loop
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; GCN-LABEL: {{^}}annotate_unreachable_noloop:
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; GCN: s_cbranch_scc1
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; GCN-NOT: s_endpgm
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; GCN: .Lfunc_end0
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define amdgpu_kernel void @annotate_unreachable_noloop(ptr addrspace(1) noalias nocapture readonly %arg) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1: ; preds = %bb
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%tmp2 = sext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x float>, ptr addrspace(1) %arg, i64 %tmp2
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%tmp4 = load <4 x float>, ptr addrspace(1) %tmp3, align 16
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br i1 undef, label %bb5, label %bb3
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bb3: ; preds = %bb1
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%tmp6 = extractelement <4 x float> %tmp4, i32 2
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%tmp7 = fcmp olt float %tmp6, 0.000000e+00
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br i1 %tmp7, label %bb4, label %bb5 ; crash goes away if these are swapped
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bb4: ; preds = %bb3
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unreachable
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bb5: ; preds = %bb3, %bb1
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unreachable
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}
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; OPT-LABEL: @annotate_ret_noloop(
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; OPT-NOT: call i1 @llvm.amdgcn.loop
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; GCN-LABEL: {{^}}annotate_ret_noloop:
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; GCN: load_dwordx4
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; GCN: v_cmp_nlt_f32
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; GCN: s_and_saveexec_b64
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; GCN-NEXT: s_endpgm
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; GCN: .Lfunc_end
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define amdgpu_kernel void @annotate_ret_noloop(ptr addrspace(1) noalias nocapture readonly %arg) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1: ; preds = %bb
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%tmp2 = sext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x float>, ptr addrspace(1) %arg, i64 %tmp2
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%tmp4 = load <4 x float>, ptr addrspace(1) %tmp3, align 16
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%tmp5 = extractelement <4 x float> %tmp4, i32 1
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store volatile <4 x float> %tmp4, ptr addrspace(1) undef
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%cmp = fcmp ogt float %tmp5, 1.0
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br i1 %cmp, label %bb5, label %bb3
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bb3: ; preds = %bb1
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%tmp6 = extractelement <4 x float> %tmp4, i32 2
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%tmp7 = fcmp olt float %tmp6, 0.000000e+00
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br i1 %tmp7, label %bb4, label %bb5 ; crash goes away if these are swapped
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bb4: ; preds = %bb3
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ret void
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bb5: ; preds = %bb3, %bb1
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ret void
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}
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; OPT-LABEL: @uniform_annotate_ret_noloop(
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; OPT-NOT: call i1 @llvm.amdgcn.loop
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; GCN-LABEL: {{^}}uniform_annotate_ret_noloop:
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; GCN: s_cbranch_scc1
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; GCN: s_endpgm
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; GCN: .Lfunc_end
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define amdgpu_kernel void @uniform_annotate_ret_noloop(ptr addrspace(1) noalias nocapture readonly %arg, i32 %tmp) #0 {
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bb:
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br label %bb1
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bb1: ; preds = %bb
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%tmp2 = sext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x float>, ptr addrspace(1) %arg, i64 %tmp2
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%tmp4 = load <4 x float>, ptr addrspace(1) %tmp3, align 16
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br i1 undef, label %bb5, label %bb3
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bb3: ; preds = %bb1
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%tmp6 = extractelement <4 x float> %tmp4, i32 2
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%tmp7 = fcmp olt float %tmp6, 0.000000e+00
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br i1 %tmp7, label %bb4, label %bb5 ; crash goes away if these are swapped
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bb4: ; preds = %bb3
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ret void
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bb5: ; preds = %bb3, %bb1
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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