9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
51 lines
1.7 KiB
YAML
51 lines
1.7 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: smrd_vgpr_offset_imm
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# GCN: V_READFIRSTLANE_B32
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# GCN: S_BUFFER_LOAD_DWORD_SGPR
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---
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name: smrd_vgpr_offset_imm
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
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%4:vgpr_32 = COPY $vgpr0
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%3:sgpr_32 = COPY $sgpr3
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%6:sreg_32_xm0 = S_MOV_B32 4095
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%8:vgpr_32 = COPY %6
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%7:vgpr_32 = V_ADD_CO_U32_e32 %4, killed %8, implicit-def dead $vcc, implicit $exec
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%10:sreg_32 = COPY %7
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%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0
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$vgpr0 = COPY %9
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SI_RETURN_TO_EPILOG $vgpr0
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...
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# GCN-LABEL: name: smrd_vgpr_offset_imm_add_u32
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# GCN: V_READFIRSTLANE_B32
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# GCN: S_BUFFER_LOAD_DWORD_SGPR
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---
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name: smrd_vgpr_offset_imm_add_u32
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
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%4:vgpr_32 = COPY $vgpr0
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%3:sgpr_32 = COPY $sgpr3
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%6:sreg_32_xm0 = S_MOV_B32 4095
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%8:vgpr_32 = COPY %6
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%7:vgpr_32 = V_ADD_U32_e32 %4, killed %8, implicit $exec
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%10:sreg_32 = COPY %7
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%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0 :: (dereferenceable invariant load (s32))
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$vgpr0 = COPY %9
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SI_RETURN_TO_EPILOG $vgpr0
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...
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